AN1042 データシートの表示（PDF） - STMicroelectronics

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AN1042

ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT

STMicroelectronics 

ST7 ROUTINE FOR I2C SLAVE MODE MANAGEMENT

1.3 TRANSFER SEQUENCING

Figure 1. I2C Slave Transfer Sequencing Diagram

7-bit Slave receiver:

S Address A

Data1

EV1

A

Data2

EV2

A

DataN

.....

EV2

A

P

EV2

EV4

7-bit Slave transmitter:

S Address A

Data1

EV1 EV3

10S-bit Slave receiver:

A

Data2

EV3

A

DataN

.....

EV3

NA

P

EV3-1

EV4

S Header A Address A

Data1

EV1

A

DataN

.....

EV2

A

P

EV2

EV4

10-bit Slave transmitter:

Sr Header A

Data1 A

.... DataN A

P

EV1 EV3

EV3 .

EV3-1

EV4

1

Legend:S=Start, P=Stop, A=Acknowledge, NA=Non-Acknowledge, EVx=Event (with interruptif ITE=1).

EV1: EVF=1, ADSL=1, cleared by reading SR1 register.

EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.

EV3_1: EVF=1, AF=1, cleared by reading SR1 register.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

In blue are events sent by the master whereas blank ones are events sent by the slave.

These frames are sequential and as the SDA line is bidirectional, this line is held sometimes

by the master and sometimes by the slave.

1.4 SLAVE EVENT FLAGS AND INTERRUPT GENERATION

Figure 2. Slave Interrupt Events Diagram

BTF

ITE

AF

ADSL

STOPF

BERR

*

* EVF can also be set by EV6 or an error from the SR2 register.

INTERRUPT

EVF

2/8

2

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