ADP3026ARU データシートの表示（PDF） - Analog Devices

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ADP3026ARU

High-Efficiency Notebook Computer Power Supply Controller

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADP3026

PWM

COMPARATOR

VRAMP

ADP3026

DRVH

DRVL

EAO

EAN

R1

REF FB

VIN

L1

VOUT

COUT

C2

C1 R2

PARASITIC

ESR

C3

R3

Figure 3. Buck Regulator Voltage Control Loop

The pulsewidth modulator transfer function is VOUT/

VEAOUT, where VEAOUT is the output voltage of the error

amplifier. That function is dominated by the impedance of

the output filter with its double-pole resonance frequency

(fLC) and a single zero at output capacitor (fESR) and the dc

gain of the modulator, equal to the input voltage divided by

the peak ramp height (VRAMP), which is equal to 1.2 V when

VIN = 12 V

fLC = 2π ×

1

LF ×COUT

(19)

fZ1

=

2π

×

1

R2

× C1

(23)

fZ2

=

2

π

×

1

(R1+ R3)×

C3

(24)

The value of the internal resistor R1 is 89 kΩ for the 3.3 V

switching regulator, and 150 kΩ for the 5 V switching regu-

lator.

Compensation Loop Design and Test Method

1. Choose the gain (R2/R1) for the desired bandwidth.

2. Place fZ1 20%–30% below fLC.

3. Place fZ2 20%–30% above fLC.

4. Place fP1 at fESR, check the output capacitor for worst-case

ESR tolerances.

5. Place fP2 at 40%–60% of oscillator frequency.

6. Estimate phase margins in full frequency range (zero fre-

quency to zero gain crossing frequency).

7. Apply the designed compensation and test the transient

response under a moderate step load change (30%–60%)

and various input voltages. Monitor the output voltage

via

oscilloscope. The voltage overshoot or undershoot should

be within 1%–3% of the nominal output, without ring-

ing and abnormal oscillation.

FESR

=

2π ×

1

ESR

× COUT

(20)

The compensation network consists of the internal error

amplifier and two external impedance networks ZIN and ZFB.

Once the application and the output filter capacitance and

ESR are chosen, the specific component values of the ex-

ternal impedance networks ZIN and ZFB can be

determined. There are two design criteria for achieving

stable switching regulator behavior within the line and load

range. One is the maximum bandwidth of the loop, which

affects fast transient response, if needed, and the other is

the minimum accepted by the design phase margin.

The phase margin is the difference between the closed-loop

phase and 180 degrees. Recommended phase margin is 45 to

60 degrees for most applications.

The equations for calculating the compensation Poles and

Zeros are:

fP1

=

2π

×

1

R2 × C1×C2

C1+ C2

fP2

=

2π

×

1

R3 × C3

(21)

(22)

Layout Considerations

The following guidelines are recommended for optimal

performance of a switching regulator in a portable PC sys-

tem:

General Recommendations

1. For best results, a four-layer (minimum) PCB is rec-

ommended. This should allow the needed versatility for

control circuitry interconnections with optimal place-

ment, a signal ground plane, power planes for both

power ground and the input power, and wide inter-

connection traces in the rest of the power delivery current

paths. Each square unit of 1 ounce copper trace has a

resistance of ~ 0.53 mý at room temperature.

2. Whenever high currents must be routed between PCB lay-

ers, vias should be used liberally to create several parallel

current paths so that the resistance and inductance in-

troduced by these current paths is minimized and the via

current rating is not exceeded.

3. The power and ground planes should overlap each

other as little as possible. It is generally easiest (al-

though not necessary) to have the power and signal

ground planes on the same PCB layer. The planes

should be connected nearest to the first input capacitor

where the input ground current flows from the con-

verter back to the battery.

REV. PrB

–17–

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