HD6433024F データシートの表示（PDF） - Hitachi -> Renesas Electronics
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HD6433024F Datasheet PDF : 824 Pages
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10.2 Register Descriptions.......................................................................................................... 309
10.2.1 Port A Data Direction Register (PADDR) ............................................................ 309
10.2.2 Port A Data Register (PADR) ............................................................................... 309
10.2.3 Port B Data Direction Register (PBDDR) ............................................................ 310
10.2.4 Port B Data Register (PBDR)................................................................................ 310
10.2.5 Next Data Register A (NDRA) ............................................................................. 311
10.2.6 Next Data Register B (NDRB).............................................................................. 313
10.2.7 Next Data Enable Register A (NDERA)............................................................... 315
10.2.8 Next Data Enable Register B (NDERB) ............................................................... 316
10.2.9 TPC Output Control Register (TPCR) .................................................................. 317
10.2.10 TPC Output Mode Register (TPMR) .................................................................... 319
10.3 Operation ............................................................................................................................ 321
10.3.1 Overview ............................................................................................................... 321
10.3.2 Output Timing ....................................................................................................... 322
10.3.3 Normal TPC Output .............................................................................................. 323
10.3.4 Non-Overlapping TPC Output .............................................................................. 325
10.3.5 TPC Output Triggering by Input Capture ............................................................. 327
10.4 Usage Notes........................................................................................................................ 328
10.4.1 Operation of TPC Output Pins .............................................................................. 328
10.4.2 Note on Non-Overlapping Output......................................................................... 328
Section 11 Watchdog Timer .............................................................................................. 331
11.1 Overview ............................................................................................................................ 331
11.1.1 Features ................................................................................................................. 331
11.1.2 Block Diagram ...................................................................................................... 332
11.1.3 Pin Configuration .................................................................................................. 332
11.1.4 Register Configuration .......................................................................................... 333
11.2 Register Descriptions.......................................................................................................... 333
11.2.1 Timer Counter (TCNT) ......................................................................................... 333
11.2.2 Timer Control/Status Register (TCSR) ................................................................. 334
11.2.3 Reset Control/Status Register (RSTCSR) ............................................................. 336
11.2.4 Notes on Register Access...................................................................................... 337
11.3 Operation ............................................................................................................................ 339
11.3.1 Watchdog Timer Operation .................................................................................. 339
11.3.2 Interval Timer Operation ...................................................................................... 340
11.3.3 Timing of Setting of Overflow Flag (OVF).......................................................... 340
11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) ................................... 341
11.4 Interrupts ............................................................................................................................ 342
11.5 Usage Notes........................................................................................................................ 342
Section 12 Serial Communication Interface ................................................................. 343
12.1 Overview ............................................................................................................................ 343
12.1.1 Features ................................................................................................................. 343
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