AD7175-8 データシートの表示（PDF） - Analog Devices
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AD7175-8
Analog Devices
AD7175-8 Datasheet PDF : 64 Pages
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AD7175-8
Data Sheet
Parameter
POWER DISSIPATION5
Full Operating Mode
Standby Mode
Power-Down Mode
Test Conditions/Comments
Min
Typ
Max
Unit
All buffers disabled, external clock and
reference, AVDD2 = 2 V, IOVDD = 2 V
All buffers disabled, external clock and
reference, all supplies = 5 V
All buffers disabled, external clock and
reference, all supplies = 5.5 V
All buffers enabled, internal clock and
reference, AVDD2 = 2 V, IOVDD = 2 V
All buffers enabled, internal clock and
reference, all supplies = 5 V
All buffers enabled, internal clock and
reference, all supplies = 5.5 V
Internal reference off, all supplies = 5 V
Internal reference on, all supplies = 5 V
Full power-down, all supplies = 5 V
21
mW
42
mW
52
mW
82
mW
105
mW
136
mW
150
µW
2.2
mW
25
50
µW
1 This specification is not production tested but is supported by characterization data at the initial product release.
2 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected. A system full-scale
calibration reduces the gain error to the order of the noise for the programmed output data rate.
3 This specification includes moisture sensitivity level (MSL) preconditioning effects.
4 The nominal range is 2 V to 5 V.
5 This specification is with no load on the REFOUT and digital output pins.
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, CLOAD = 20 pF, unless otherwise noted.
Table 2.
Parameter
SCLK
t3
t4
READ OPERATION
t1
t23
t55
t6
t7
WRITE OPERATION
t8
t9
t10
t11
Limit at TMIN, TMAX
25
25
0
15
40
0
12.5
25
2.5
20
0
10
0
8
8
5
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
Description1, 2
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay4
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high/low
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
1 Sample tested during initial release to ensure compliance.
2 See Figure 2 and Figure 3.
3 This parameter is defined as the time required for the output to cross the VOL or VOH limits.
4 The SCLK active edge is the falling edge of SCLK.
5 DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required,
while DOUT/RDY is high, although care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is
enabled, the digital word can be read only once.
Rev. 0 | Page 6 of 64
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