AD9954(Rev0) データシートの表示（PDF） - Analog Devices
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AD9954 Datasheet PDF : 36 Pages
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AD9954
Amplitude Ramp Rate (ARR)
The ARR register stores the 8-bit amplitude ramp rate used in
the auto OSK mode. This register programs the rate at which
the amplitude scale factor counter increments or decrements. If
the OSK is set to manual mode, or if OSK enable is cleared, this
register has no effect on device operation.
Frequency Tuning Word 0 (FTW0)
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role is dependent on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. This offset value is added to the output of the phase
accumulator to offset the current phase of the output signal.
The exact value of phase offset is given by the following formula
Φ
=
⎜⎝⎛
POW
214
⎟⎠⎞
×
360°
When the RAM enable bit is set, CFR1<31> = 1, and the RAM
destination is cleared, CFR1<30> = 0, the RAM supplies the
phase offset word and this register has no effect on device
operation.
Frequency Tuning Word 1 (FTW1)
The frequency tuning word is a 32-bit register that sets the
upper frequency in a linear sweep operation.
Negative and Positive Linear Sweep Control Word (NLSCW,
PLSCW)
Registers 0x07 and 0x08 are multifunctional registers. When the
linear sweep bit CFR1<21> is enabled, Register 0x07 acts as the
negative linear sweep control word (NLSCW) and Register 0x08
acts as the positive linear sweep control word (PLSCW). Each of
the linear sweep control words contains a 32-bit delta frequency
tuning word (FDFTW, RDFTW) and an 8-bit sweep ramp rate
word (FSRRW, RSRRW). The delta frequency tuning words
determine the amount the frequency accumulator will incre-
ment or decrement the resultant tuning word. The sweep ramp
rate words determine the rate at which the accumulator will
increment or decrement, in number of synchronization clock
cycles.
RAM Segment Control Words (RSCW0, RSCW1, RSCW2,
RSCW3)
When the Linear Sweep Enable bit CFR1<21> is clear,
Registers 0x07, 0x08, 0x09, and 0x0A act as the RAM segment
control words for each of the RAM segments. Each of the RAM
segment control words is comprised of a RAM segment address
ramp rate, a final address value, a beginning address value, a
RAM segment mode control, and a No-Dwell Bit.
RAM Segment Address Ramp Rate, RSCW<39:24>
For RAM modes that step through address values, such as
ramping, this 16-bit word defines the number of SYNC_CLK
cycles the RAM controller dwells at each address. A value of 0 is
invalid. Any other value from 1 to 65535 may be used.
RAM Segment Final Address RSCW<9:8>, RSCW<23:16>
This discontinuous 10-bit sequence defines the final address
value for the given RAM segment. The order in which the bits
are listed is the order in which the bits must be written.
RSCW<23>, even though during the write operation is more
significant than RSCW<9>, is only the third MSB of the final
address value. RSCW<9>, even though it comes later in the
RSCW than RSCW<23>, is the MSB of the final address value.
RAM Segment Beginning Address RSCW<3:0>, <15:10>
This discontinuous 10-bit sequence defines the final address
value for the given RAM segment. The order in which the bits
are listed is the order in which the bits must be written.
RSCW<15>, even though during the write operation is more
significant than RSCW<3>, is only the fifth MSB of the final
address value. RSCW<3>, even though it comes later in the
RSCW than RSCW<15>, is the MSB of the final address value.
RAM Segment Mode Control RSCW<7:5>
This 3-bit sequence determines the RAM segment’s mode of
operation. There are only five possible RAM modes, so only
values of 0–5 are valid. See Table 9 to determine the bit combi-
nation for various RAM modes.
RAM Segment No-Dwell Bit RSCW<4>
This bit sets the No-Dwell feature of sweeping profiles. In pro-
files that sweep from a defined beginning to a defined end, the
RAM controller can either dwell at the final address until the
next profile is selected or, when this bit is set, the RAM control-
ler will return to the beginning address and dwell there until the
next profile is selected.
RAM
The AD9954 incorporates a 1024 × 32 block of SRAM. The
RAM is a bidirectional single-port. Both read and write opera-
tions from and to the RAM are valid, but they cannot occur
simultaneously. Write operations from the serial I/O port have
precedence, and if an attempt to write to RAM is made during a
read operation, the read operation will be halted. The RAM is
controlled in multiple ways, dictated by the modes of operation
described in the RAM Segment Control Word <7:5> as well as
data in the control function register. Read/write control for the
RAM will be described for each mode supported.
When the RAM enable bit (CFR1<31>) is set, the RAM output
optionally drives the input to the phase accumulator or the
phase offset adder, depending on the state of the RAM destina-
Rev. 0 | Page 21 of 36
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