AD9954(Rev0) データシートの表示（PDF） - Analog Devices
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AD9954 Datasheet PDF : 36 Pages
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AD9954
Parameter
Maximum Data Valid Time
Wake-Up Time4
Minimum Reset Pulse Width High
I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time
Latency
I/O UPDATE to Frequency Change Prop Delay
I/O UPDATE to Phase Offset Change Prop Delay
I/O UPDATE to Amplitude Change Prop Delay
PS0, PS1 to RAM Driven Frequency Change Prop Delay
PS0, PS1 to RAM Driven Phase Change Prop Delay
PS0 to Linear Frequency Sweep Prop Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single Tone Mode (Comparator Off)
With RAM or Linear Sweep Enabled
With Comparator Enabled
With RAM and Comparator Enabled
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION6
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution7
Test
Temp Level Min
FULL IV
FULL IV
FULL IV
5
FULL I
4
FULL I
6
FULL I
0
25°C IV
24
25°C IV
24
25°C IV
16
25°C IV
28
25°C IV
28
25°C IV
28
25°C I
1.25
25°C I
25°C I
2.2
25°C I
25°C V
25°C
25°C
25°C I
1.35
25°C I
25°C I
2.8
25°C I
25°C I
25°C I
25°C I
25°C I
25°C I
25°C I
25°C VI
62.5
25°C VI
100
25°C V
Typ Max
25
1
0.6
0.8
3
12
12
2
0.4
0.4
162 171
175 190
180 190
198 220
150 160
20
27
±1
Unit
ns
ms
SYSCLK Cycles5
ns
ns
ns
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
V
V
V
V
µA
µA
pF
V
V
V
V
mW
mW
mW
mW
mW
mW
MHz
MHz
SYSCLK Cycles
1 To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-
formance of the device.
2 Represents the cycle-to-cycle residual jitter from the comparator alone.
3 Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4 Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The longest time required is for the reference
clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.
5 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-
quency is the same as the external reference clock frequency.
6 SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
7 This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
Rev. 0 | Page 6 of 36
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