CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
Logic Block Diagram (CY7C1510KV18)
D[7:0]
8
A(21:0) 22
Address
Register
Write
Reg
Write
Reg
K
K
DOFF
VREF
WPS
NWS[1:0]
CLK
Gen.
Control
Logic
Read Data Reg.
16
8
8
Address
Register
22
A(21:0)
Control
Logic
RPS
C
C
Reg.
Reg. 8
Reg.
8
8
CQ
CQ
Q[7:0]
Logic Block Diagram (CY7C1525KV18)
D[8:0]
9
A(21:0) 22
Address
Register
Write
Reg
Write
Reg
K
K
DOFF
VREF
WPS
BWS[0]
CLK
Gen.
Control
Logic
Read Data Reg.
18
9
9
Address
Register
22
A(21:0)
Control
Logic
RPS
C
C
Reg.
Reg. 9
Reg.
9
9
CQ
CQ
Q[8:0]
Document Number: 001-00436 Rev. *M
Page 2 of 33
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