Logic Block Diagram (CY7C1512KV18)
CY7C1510KV18, CY7C1525KV18
CY7C1512KV18, CY7C1514KV18
D[17:0]
18
A(20:0) 21
Address
Register
K
K
DOFF
VREF
WPS
BWS[1:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
21
A(20:0)
Read Data Reg.
36
18
18
Control
Logic
RPS
C
C
Reg.
Reg. 18
Reg.
18
18
CQ
CQ
Q[17:0]
Logic Block Diagram (CY7C1514KV18)
D[35:0]
36
A(19:0) 20
Address
Register
K
K
DOFF
VREF
WPS
BWS[3:0]
CLK
Gen.
Control
Logic
Write
Reg
Write
Reg
Address
Register
20
A(19:0)
Read Data Reg.
72
36
36
Control
Logic
RPS
C
C
Reg.
Reg. 36
Reg.
36
36
CQ
CQ
Q[35:0]
Document Number: 001-00436 Rev. *E
Page 3 of 30
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