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CY7C1462AV33(2004) データシートの表示(PDF) - Cypress Semiconductor
部品番号
コンポーネント説明
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CY7C1462AV33
(Rev.:2004)
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL™ Architecture
Cypress Semiconductor
CY7C1462AV33 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
Logic Block Diagram-CY7C1462AV33 (2 Mbit x 18)
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
D1
Q1
A1'
A0
D0
BURST
Q0
A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
O
U
T
S
E
N
P
U
T
S
MEMORY
E
ARRAY
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
D
P
A
U
T
T
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
G
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
DQs
DQP
a
DQP
b
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Logic Block Diagram-CY7C1464AV33 (512K x 72)
A0, A1, A
MODE
CLK
C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1
D1
Q1
A1'
A0
D0
BURST
Q0
A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
O
U
T
S
E
N
P
U
T
WRITE
DRIVERS
S
MEMORY
E
ARRAY
A
M
P
S
R
E
G
I
S
T
E
R
S
E
O
U
T
D
P
A
U
T
T
A
B
S
U
T
F
E
F
E
E
R
R
I
S
N
G
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
DQs
DQP
a
DQP
b
DQP
c
DQP
d
DQP
e
DQP
f
DQP
g
DQP
h
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Selection Guide
CY7C1460AV33-250
CY7C1462AV33-250
CY7C1464AV33-250
CY7C1460AV33-200
CY7C1462AV33-200
CY7C1464AV33-200
CY7C1460AV33-167
CY7C1462AV33-167
CY7C1464AV33-167
Maximum Access Time
2.6
3.2
3.4
Maximum Operating Current
475
425
375
Maximum CMOS Standby
100
100
100
Current
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Unit
ns
mA
mA
Document #: 38-05353 Rev. *A
Page 2 of 27
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