CY7C1462AV33(2004) データシートの表示（PDF） - Cypress Semiconductor
部品番号
コンポーネント説明
メーカー
CY7C1462AV33
(Rev.:2004)
(Rev.:2004)
Cypress Semiconductor
CY7C1462AV33 Datasheet PDF : 27 Pages
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PRELIMINARY
CY7C1460AV33
CY7C1462AV33
CY7C1464AV33
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1464AV33 , BWa,b,c,d for CY7C1460AV33 and BWa,b for
CY7C1462AV33) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
A1,A0
A1,A0
A1,A0
00
01
10
01
00
11
10
11
00
11
10
01
Linear Burst Address Table (MODE = GND)
First
Address
A1,A0
00
01
10
11
Second
Address
A1,A0
01
10
11
00
Third
Address
A1,A0
10
11
00
01
Fourth
Address
A1,A0
11
10
01
00
Fourth
Address
A1,A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
2tCYC
0
Max
100
2tCYC
2tCYC
Unit
mA
ns
ns
ns
ns
Truth Table[1, 2, 3, 4, 5, 6, 7]
Operation
Deselect Cycle
Address
Used CE ZZ ADV/LD WE BWx OE CEN CLK
None
HL
L
X XX L
L-H
Continue
Deselect Cycle
None
XL
H
X XX L
L-H
Read Cycle
(Begin Burst)
External
LL
L
H XL L
L-H
Read Cycle
(Continue Burst)
Next
XL
H
X XL L
L-H
NOP/Dummy Read External
(Begin Burst)
LL
L
H XH L
L-H
Dummy Read
(Continue Burst)
Next
XL
H
X XH L
L-H
Write Cycle
(Begin Burst)
External
LL
L
L LX L
L-H
Write Cycle
(Continue Burst)
Next
XL
H
X LX L
L-H
NOP/WRITE ABORT None
(Begin Burst)
LL
L
L HX L
L-H
WRITE ABORT
(Continue Burst)
Next
XL
H
X HX L
L-H
DQ
Tri-State
Tri-State
Data Out (Q)
Data Out (Q)
Tri-State
Tri-State
Data In (D)
Data In (D)
Tri-State
Tri-State
Document #: 38-05353 Rev. *A
Page 8 of 27
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