CY14B108N-ZSP25XCT データシートの表示（PDF） - Cypress Semiconductor

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CY14B108N-ZSP25XCT

8 Mbit (1024K x 8/512K x 16) nvSRAM

Cypress Semiconductor 

Address

CE

BHE, BLE

WE

Data Input

Data Output

CY14B108L, CY14B108N

Figure 8. SRAM Write Cycle #2: CE Controlled[3, 13, 14, 15]

tWC

Address Valid

tSA

tSCE

tHA

tBW

tPWE

tSD

tHD

Input Data Valid

High Impedance

Address

CE

BHE, BLE

WE

Data Input

Data Output

Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled[3, 13, 14, 15]

tWC

Address Valid

tSCE

tSA

tBW

tHA

tAW

tPWE

tSD

tHD

Input Data Valid

High Impedance

Document #: 001-45523 Rev. *D

Page 12 of 24

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