NCV8851BDBGEVB
VIN
VIN
12
EN
11
VIN_IC
3
ROSC
ROSC
20
SYNC
1
CC2
CCOMP
15
CC1
RC1
CFB
16
CSOUT
17
6VOUT
9
DBST
BST
4
Q1
GH
5
VSW
6
Q2
GL
7
PGND
8
+
VIN
−
CBST
RS
L
2 VIN_CS
CSP
19
CSN
18
VFB
13
CV2
VCOMP
RV1
14
CV1
10
AGND
+
C
VOUT
−
RF1
RF0
Figure 2. NCV8851B Application Diagram
Operational Guidelines
1. Connect a dc input voltage, 4.5 V ≤ VBATT ≤ 40 V,
between “VIN” and “GND”.
2. Connect a load impedance between “VOUT” and
“GND”.
3. Connect a dc enable voltage, 4.5 V ≤ EN ≤ VBATT
≤ 20 V, between “EN” and “GND”. If EN must be
tied to a higher voltage, a current limiting resistor
is required (see below).
V BATT
4. Optionally, for external clock synchronization,
connect a pulse source, SYNC, between “SYNC”
and “GND”. The positive amplitude should be
1.0 V ≤ SYNC ≤ 7.0 V and negative amplitude
should be -0.3 V ≤ GND ≤ 0.8 V. SYNC pulse
duty cycle may range from 10% to 90%, and
frequency may range from the programmed
frequency (170 kHz by default) to 600 kHz.
V OUT
SYNC
EN
Figure 3. Evaluation Board Connections
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3