ST72P611F1M1 データシートの表示（PDF） - STMicroelectronics

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ST72P611F1M1

LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH MEMORY, LVD, WDG, TIMER

STMicroelectronics 

ST7261

5 RESET AND CLOCK MANAGEMENT

5.1 RESET

The Reset procedure is used to provide an orderly

software start-up or to exit low power modes.

Three reset modes are provided: a low voltage re-

set, a watchdog reset and an external reset at the

RESET pin.

A reset causes the reset vector to be fetched from

addresses FFFEh and FFFFh in order to be loaded

into the PC and with program execution starting

from this point.

An internal circuitry provides a 514 CPU clock cy-

cle delay from the time that the oscillator becomes

active.

5.1.1 Low Voltage Reset

Low voltage reset circuitry generates a reset when

VDD is:

s below VIT+ when VDD is rising,

s below VIT- when VDD is falling.

During low voltage reset, the RESET pin is held low,

thus permitting the MCU to reset other devices.

The Low Voltage Detector can be disabled by set-

ting the LVD bit of the Option byte.

5.1.3 External Reset

The external reset is an active low input signal ap-

plied to the RESET pin of the MCU.

As shown in Figure 13, the RESET signal must

stay low for a minimum of one and a half CPU

clock cycles.

An internal Schmitt trigger at the RESET pin is pro-

vided to improve noise immunity.

Figure 10. Low Voltage Reset functional Diagram

RESET

VDD

LOW VOLTAGE

RESET

FROM

WATCHDOG

RESET

INTERNAL

RESET

Figure 11. Low Voltage Reset Signal Output

VIT+

VIT-

VDD

5.1.2 Watchdog Reset

When a watchdog reset occurs, the RESET pin is

pulled low permitting the MCU to reset other devic-

es as when low voltage reset (Figure 10).

RESET

Note: Typical hysteresis (VIT+-VIT-) of 250 mV is

expected

Figure 12. Temporization timing diagram after an internal Reset

VDD

VIT+

Addresses

temporization (514 CPU clock cycles)

$FFFE

17/71

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