ST7261
INTERRUPTS (Cont’d)
Figure 18. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
FETCH NEXT INSTR UCTION
N
INTE RRUPT
PENDING ?
Y
N
EXECU TE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTO R
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 5. Interrupt Mapping
N°
Source
Block
Description
Reset Vector
TRAP software interrupt vector
0
ICP
FLASH Start programming NMI interrupt
vector
1
USB
USB End Suspend interrupt vector
2
Port A external interrupts IT[3:1]
I/O Ports
3
Port B external interrupts IT[8:5]
4
NOT USED
5
TBU
Timebase Unit interrupt vector
6
NOT USED
7
NOT USED
8
NOT USED
9
USB
USB interrupt vector
10
NOT USED
Register
Label
Exit
from
HALT
Yes
No
Yes
Address
Vector
Priority
Order
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh -FFFB h
Highest
Priority
USBISTR Yes FFF8h-FFF9h
Yes
ITRFRE1
Yes
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
TBUCSR No FFF0h-FFF1h
F FEEh-FFE Fh
FFECh-FFEDh
F FEAh -FFEB h
Lowest
USBISTR No FFE8h-FFE9h Priority
FFE6h-FFE7h
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