LTC2919 データシートの表示（PDF） - Analog Devices
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LTC2919 Datasheet PDF : 20 Pages
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LTC2919
PIN FUNCTIONS (DFN/MSOP)
SEL (Pin 1): Input Polarity Select Three-State Input.
Connect to VCC, GND or leave unconnected in open state
to select one of three possible input polarity combinations
(refer to Table 1).
VCC (Pin 2): Power Supply. Bypass this pin to ground with
a 0.1μF (or greater) capacitor. Operates as a direct supply
input for voltages up to 6V. Operates as a shunt regulator
for supply voltages greater than 6V and should have a
resistor between this pin and the supply to limit VCC input
current to no greater than 10mA. When used without a
current-limiting resistor, pin voltage must not exceed 6V.
UVLO options allow VCC to be used as an accurate third
fixed -10% UV supply monitor.
OUT1 (Pin 3): Open-Drain Logic Output 1. Asserts low
when positive polarity ADJ1 voltage is below threshold or
negative polarity ADJ1 voltage is above threshold. Requires
an external pull-up resistor and may be pulled above VCC.
OUT2 (Pin 4): Open-Drain Logic Output 2. Asserts low
when positive polarity ADJ2 voltage is below threshold
or negative polarity ADJ2 voltage is above threshold.
Requires an external pull-up resistor and may be pulled
above VCC.
RST (Pin 5): Open-Drain Inverted Reset Logic Output.
Asserts low when any positive polarity input voltage is
below threshold or any negative polarity input voltage is
above threshold or VCC is below UVLO threshold. Held
low for a timeout period after all voltage inputs are valid.
Requires an external pull-up resistor and may be pulled
above VCC.
GND (Pin 6): Device Ground.
REF (Pin 7): Buffered Reference Output. 1V nominal refer-
ence used for the offset of negative-monitoring applica-
tions. The buffered reference can source and sink up to
1mA. The reference can drive a capacitive load of up to
1000pF. Larger capacitance may degrade transient per-
formance. This pin does not require a bypass capacitor,
nor is one recommended. Leave open if unused.
TMR (Pin 8): Reset Timeout Control. Attach an external
capacitor (CTMR) to GND to set a reset timeout period
of 9ms/nF. A low leakage ceramic capacitor is recom-
mended for timer accuracy. Capacitors larger than 1μF
(9 second timeout) are not recommended. See
Applications Information for further details. Leaving this
pin open generates a minimum timeout of approximately
400μs. A 2.2nF capacitor will generate a 20ms timeout.
Tying this pin to ground will enable the internal 200ms
timeout. Tying this pin to VCC will disable the reset timer
and put the part in comparator mode. Signals from the
comparator outputs will then go directly to RST.
ADJ2 (Pin 9): Adjustable Voltage Input 2. Input to volt-
age monitor comparator 2 (0.5V nominal threshold). The
polarity of the input is selected by the state of the SEL
pin (refer to Table 1). Tie to GND if unused (with SEL =
GND or Open).
ADJ1 (Pin 10): Adjustable Voltage Input 1. Input to volt-
age monitor comparator 1 (0.5V nominal threshold). The
polarity of the input is selected by the state of the SEL
pin (refer to Table 1). Tie to REF if unused (with SEL =
VCC or Open).
Exposed Pad (Pin 11, DFN Only): The Exposed Pad may
be left unconnected. For better thermal contact, tie to a
PCB trace. This trace must be grounded or unconnected.
Rev. A
For more information www.analog.com
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