ADSP-BF538BBCZ-4A データシートの表示（PDF） - Analog Devices

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ADSP-BF538BBCZ-4A

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF538/ADSP-BF538F

Table 3. System and Core Event Mapping (Continued)

Event Source

DMA18 Interrupt (UART2 RX)

DMA19 Interrupt (UART2 TX)

Timer0, Timer1, Timer2 Interrupts

TWI0 Interrupt

TWI1 Interrupt

CAN Receive Interrupt

CAN Transmit Interrupt

Port F GPIO Interrupts A and B

MDMA0 Stream 0 Interrupt

MDMA0 Stream 1 Interrupt

MDMA1 Stream 0 Interrupt

MDMA1 Stream 1 Interrupt

Software Watchdog Timer

Core

Event Name

IVG10

IVG10

IVG11

IVG11

IVG11

IVG11

IVG11

IVG12

IVG13

IVG13

IVG13

IVG13

IVG13

Event Control

The ADSP-BF538/ADSP-BF538F processors provide the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 16 bits wide:

• CEC interrupt latch register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may also be written to clear (cancel) latched events. This

register may be read while in supervisor mode and may

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

• CEC interrupt mask register (IMASK) – The IMASK regis-

ter controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event, pre-

venting the processor from servicing the event even though

the event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. (Note

that general-purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.)

• CEC interrupt pending register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 7.

Preliminary Technical Data

• SIC interrupt mask registers (SIC_IMASKx)– These regis-

ters control the masking and unmasking of each peripheral

interrupt event. When a bit is set in these registers, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in these registers masks

the peripheral event, preventing the processor from servic-

ing the event.

• SIC interrupt status registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• SIC interrupt wakeup enable registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 12.)

Because multiple interrupt sources can map to a single general-

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general-

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF538/ADSP-BF538F processors have multiple,

independent DMA controllers that support automated data

transfers with minimal overhead for the processor core. DMA

transfers can occur between the processor internal memories

and any of its DMA capable peripherals. Additionally, DMA

transfers can be accomplished between any of the DMA capable

peripherals and external devices connected to the external

memory interfaces, including the SDRAM controller and the

asynchronous memory controller. DMA capable peripherals

include the SPORTs, SPI port, UART, and PPI. Each individual

DMA capable peripheral has at least one dedicated DMA

channel.

The DMA controllers support both 1-dimensional (1D) and 2-

dimensional (2D) DMA transfers. DMA transfer initialization

can be implemented from registers or from sets of parameters

called descriptor blocks.

The 2D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to ±32K elements. Furthermore, the

column step size can be less than the row step size, allowing

Rev. PrD | Page 8 of 56 | May 2006

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