GS84118AB-133I データシートの表示（PDF） - Giga Semiconductor
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GS84118AB-133I Datasheet PDF : 27 Pages
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GS84118AT/B-166/150/130/100
Test Mode Description
Functional Description
The GS84118A provides JTAG boundary scan interface using IEEE standard 1149.1 protocol. The Test mode is intended to
provide a mechanism for testing the interconnect between master (processor, controller, etc.), SRAM, other components and the
Printed Circuit Board.
Test Access Port (TAP)
Four pins (as defined in Pin Description Tables) are used to performed JTAG functions. TDI input is used to scan test data serially
into one of three registers (Instruction Register, Boundary Scan Register and Bypass Register). TDO is the output pin to serially
output scan test data. The TDI sends the data into the LSB of the selected register and the MSB of that register feeds the data to
TDO. TMS input pin controls the state transition of 16 state TAP controllers, as specified in IEEE standard 1149.1. Inputs on TDI
and TMS are registered on the rising edge of TCK clock, and the output data on TDO is presented on the falling edge of TCK. The
TDO driver is in active state only when TAP controller is in Shift-IR state or in Shift -DR state.
TAP Controller
Sixteen state controllers are implemented as specified in IEEE standard 1149.1.
The controller enters the Reset state either through
• Power up or
• Apply logic 1 on TMS input pin on 5 consecutive rising edges.
1
Test Logic Reset
Tap Controller State Diagram
0
0 Run Test Idle 1
Select DR
1
Select IR
1
0
1 Capture DR
0
0
1
Capture IR
0
0
Shift DR
1
0
Shift IR
1
1
Exit1 DR
1
Exit1 IR
0
0
Pause DR
1
0
Exit2 DR
1
0
0
Pause IR
1
0
Exit2 IR
1
Update DR
1
0
Update IR
1
0
Rev: 1.00 9/2002
21/27
© 2002, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
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