A40MX02-TQ100 データシートの表示（PDF） - Actel Corporation

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A40MX02-TQ100

40MX and 42MX FPGA Families

Actel Corporation 

40MX and 42MX FPGA Families

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out

pin. The serial pins are used to serially connect all the

boundary-scan register cells in a device into a boundary-

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic tile and the input, output and control

ports of an I/O buffer to capture and load data into the

register to control or observe the logic state of each I/O.

JTAG

TMS

TCK

JTAG

TDI

Boundary Scan Register

Control Logic

Bypass

Register

TAP Controller

Instruction

Decode

Instruction

Register

Output

MUX

TDO

Figure 1-14 • 42MX IEEE 1149.1 Boundary Scan Circuitry

Table 3 • Test Access Port Descriptions

Port

Description

TMS (Test Mode Serial input for the test logic control bits. Data is captured on the rising edge of the test logic clock (TCK).

Select)

TCK (Test Clock Input) Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on the rising edge

of the clock, and serially to shift the output data on the falling edge of the clock. The maximum clock frequency

for TCK is 20 MHz.

TDI (Test Data Input) Serial input for instruction and test data. Data is captured on the rising edge of the test logic clock.

TDO (Test Data Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive state (high

Output)

impedance) when data scanning is not in progress.

Table 4 • Supported BST Public Instructions

Instruction

IR Code (IR2.IR0) Instruction Type

Description

EXTEST

000

Mandatory

Allows the external circuitry and board-level interconnections to

be tested by forcing a test pattern at the output pins and

capturing test results at the input pins.

SAMPLE/PRELOAD

001

Mandatory

Allows a snapshot of the signals at the device pins to be

captured and examined during operation

HIGH Z

101

Optional

Tristates all I/Os to allow external signals to drive pins. Please

refer to the IEEE Standard 1149.1 specification.

CLAMP

110

Optional

Allows state of signals driven from component pins to be

determined from the Boundary-Scan Register. Please refer to

the IEEE Standard 1149.1 specification for details.

BYPASS

111

Mandatory

Enables the bypass register between the TDI and TDO pins. The

test data passes through the selected device to adjacent devices

in the test chain.

v6.0

1-11

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