A8425 データシートの表示（PDF） - Allegro MicroSystems

部品番号

コンポーネント説明

メーカー

A8425

High Current Photoflash Capacitor Charger with IGBT Driver for Two Li+ Batteries

Allegro MicroSystems 

A8425

High Current Photoflash Capacitor Charger

with IGBT Driver for Two Li+ Batteries

charging time. Minimum-voltage switching is shown

in figure 3.

During Fast-Charging Mode, when VOUT is high

enough such that the reflected voltage (VOUT / N) is

greater than VBAT, true zero-voltage switching (ZVS)

is achieved. This further improves efficiency as well

as reduces switching noise. A ZVS interval is shown in

figure 4.

Selection of Switching Current Limit

The A8425 features continuously adjustable peak

switching current between 1.0 and 3.2 A. This is done

by selecting the value of the external resistor RSET

(connected between the ISET pin and GND), which

determines the ISET bias current, and therefore the

switching current limit, ISWlim.

To the first order approximation, ISWlim is related to

ISET and RSET by the following equation:

VSW

VOUT

VBAT

ISW

t = 1 μs/div; VOUT =10 V/div; VBAT =2 V/div.; VSW =2 V/div;

ISW =200 mA/div. VIN = 3.6 V; VBAT =5.5 V; RSET = 66.5 kΩ;

Transformer LP= 7.5 μH, N = 10

Figure 3. Fast Charging Mode, minimum voltage

ISWlim = ISET × K

= (VSET × RSET ) × K ,

(6)

where VSET = 1.2 V, K = 59000 when the IC bias volt-

age, VIN , is 3.6 V.

In real applications, the switching current limit is

affected by bias voltage, battery voltage, and the

transformer primary inductance, LP. If necessary, the

following expressions can be used to determine ISWlim

more accurately:

ISET = VSET / (RSET + RSET(INT) – K × RG(INT) ) ,(7)

VOUT

VSW

where RSET(INT) is the internal resistance of the ISET

pin (330 Ω typical), RG(INT) is the internal resistance

of the bonding wire for the GND pin (27 mΩ typical),

VBAT

and:

ISW

t = 1 μs/div; VOUT =10 V/div; VBAT =2 V/div.; VSW =2 V/div;

ISW =200 mA/div. VIN = 3.6 V; VBAT =5.5 V; RSET = 66.5 kΩ;

Transformer LP= 7.5 μH, N = 10

Figure 4. Zero-voltage switching

ISWlim = ISET × (K' + VIN × K")

+ (VBAT / LP ) × td ,

(8)

where K' = 47500, K" ≈ 3500 at TA= 25°C, and td is

the delay in SW turn-off (0.1 μs typical).

Figure 5 can be used to determine the relationship

between RSET and ISWlim at various bias voltages.

Allegro MicroSystems, Inc.

11

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Share Link: