MAX793RCSE データシートの表示（PDF） - Maxim Integrated

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MAX793RCSE

3.0V/3.3V Adjustable Microprocessor Supervisory Circuits

Maxim Integrated 

3.0V/3.3V Adjustable Microprocessor

Supervisory Circuits

MAX793

MAX794

MAX795

CHIP-ENABLE

OUTPUT

CONTROL

RESET

GENERATOR

P

CE IN

N

OUT

P

CE OUT

Figure 7. Chip-Enable Transmission Gate

The CE transmission gate remains disabled and CE IN

remains high impedance (regardless of CE IN activity)

for the first half of the reset timeout period (tRP / 2), any

time a reset is generated. While disabled, CE IN is high

impedance. When the CE transmission gate is enabled,

the impedance of CE IN appears as a 46Ω resistor in

series with the load at CE OUT.

The propagation delay through the CE transmission

gate depends on VCC, the source impedance of the

drive connected to CE IN, and the loading on CE OUT.

The CE propagation delay is production tested from the

50% point on CE IN to the 50% point on CE OUT using

a 50Ω driver and 50pF of load capacitance (Figure 9).

For minimum propagation delay, minimize the capaci-

tive load at CE OUT and use a low-output-impedance

driver.

Chip-Enable Output

When the CE transmission gate is enabled, the imped-

ance of CE OUT is equivalent to a 46Ω resistor in series

with the source driving CE IN. In the disabled mode,

the transmission gate is off and an active pullup con-

nects CE OUT to OUT (Figure 8). This pullup turns off

when the transmission gate is enabled.

Early Power-Fail Warning

(MAX793/MAX794)

Critical systems often require an early warning indicat-

ing that power is failing. This warning provides time for

the µP to store vital data and take care of any additional

“housekeeping” functions, before the power supply

gets too far out of tolerance for the µP to operate reli-

ably. The MAX793/MAX794 offer two methods of

achieving this early warning. If access to the unregulat-

ed supply is feasible, the power-fail comparator input

(PFI) can be connected to the unregulated supply

through a voltage divider, with the power-fail compara-

tor output (PFO) providing the NMI to the µP (Figure

VRST

VCC

VRST

VRST

VSW

VRST

VSW

CE OUT

VBATT

tRP/2

10µs VBATT

VCC

tRP

RESET

(PULLED TO VCC)

CE IN

VBATT = 3.6V

RESET PULLED UP TO VCC

Figure 8. Chip-Enable Timing

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