LTC692 データシートの表示（PDF） - Linear Technology
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LTC692 Datasheet PDF : 20 Pages
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LTC692/LTC693
APPLICATIONS INFORMATION
5V
0.1μF
3V
VCC
VOUT
LTC693
CE OUT
VBATT
GND
CE IN
RESET
RESET
+
10μF
0.1μF
20ns PROPAGATION DELAY
FROM DECODER
VCC
62512
RAM
CSGND
692_3 • F06
TO μP
Figure 6. A Typical Nonvolatile CMOS RAM Application
5V
0.1μF
3V
VCC
VOUT
LTC692
VBATT RESET
GND
+
10μF
0.1μF
CS
VCC
62128
RAM
CS1
CS2
GND
692_3 • F07
Figure 7. Write Protect for RAM with the LTC692
Power Fail Warning
The LTC692/LTC693 generate a power failure output
(PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
power failure input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The volt-
age divider ratio can be chosen such that the voltage at
the PFI pin falls below 1.3V, several milliseconds before
the 5V supply falls below the maximum reset voltage
threshold of 4.50V. PFO is normally used to interrupt the
microprocessor to execute shutdown procedure between
PFO and RESET or RESET.
The power fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the sum-
ming junction at the PFI pin.
VH
=
1.3V
⎛
⎝⎜
1+
R1
R2
+
R1⎞
R3 ⎠⎟
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
VL
=
1.3V
⎛
⎝⎜
1+
R1
R2
–
(5V – 1.3V)R1⎞
1.3V(R3 + R4)⎠⎟
Assuming
R4
<<
R3,VHYSTERESIS
=
5V
R1
R3
0692fa
12
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