MAR281F データシートの表示（PDF） - Dynex Semiconductor

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MAR281F

MIL-STD-1750A Microprocessor

Dynex Semiconductor 

MAS281

which is decoded by the MAS281 but is treated, in some ways,

like an externally implemented XIO command. This exception

is discussed below.

Internal l/O transfers involve all XIO commands which are

decoded internally either by the MAS281 or by the MA31751

MMU/BPU chip (with the exception noted above). Table 7b

identifies these commands. The A, Dl and DO registers are

used as in operand transfers. Internal l/O transfers are

characterised by DDN staying high for the duration of the

transfer in order to prevent bus contention between the module

AD bus and the system bus. Machine cycle associated with

internal I/O commands are normally six oscillator cycles in

duration but might be extended to seven OSC cycles by the

internal ready interface if the module is run at high frequencies.

Internal I/O transfers may be subdivided into writes, reads and

commands as follows:

I/O writes consist of a command phase followed by the

value to be written. The command is placed on the AD bus

from the A register at the SYNCN high-to-low transition and is

assured valid on the high-to-low transition of AS. The value to

be written is placed on the AD bus from the DO register at the

SYNCN low-to-high transition and is written to the internal l/O

device by the subsequent SYNCN high-to-low transition. An

example of an internal l/O write is loading timer A.

I/O reads consist of a command phase followed by the

value returned by the internal device. The command is placed

on the AD bus from the A register at the SYNCN high-to-low

transition and is assured valid on the highto-low transition of

AS. The internal l/O device places the value to be read on the

AD bus at the SYNCN low-tohigh transition. This value is

captured by the Dl register on the subsequent SYNCN high-to-

low transition. An example of such an operation is reading the

interrupt mask register.

I/O commands consist of a command phase alone. The

command is placed on the AD bus from the A register at the

SYNCN high-to-low transition and is executed at the following

SYNCN high-to-low transition. An example of an l/O command

is raising the DMAE discrete.

External l/O transfers are similar to internal l/O transfers

with the following exceptions: (1) DDN goes low, as with

operand transfers, during an l/O read; and (2) external l/O

machine cycles are normally five OSC cycles in duration and

may be extended via the RDYN signal as with operand

transfers.

As discussed earlier, the Read Configuration Word

command is a special case. It is decoded internally to generate

a read strobe (CONFWN) and therefore uses both the

standard internal I/O six OSC period machine cycle as well as

the internal ready interface to extend its cycle. It relies on an

externally implemented configuration register, however, and

therefore cycles DDN as with external I/O cycles. Therefore,

the configuration word register must reside on the system side

of the data bus transceivers as opposed to residing directly on

the local AD bus (as shown in Figure 5).

Nine user interrupt request inputs are provided for

programmed response to asynchronous system events. A low

on any of these inputs will be detected at the high-to-low

transition of SYNCN and latched into the Pending Interrupt (Pl)

BIT Test Coverage

1

Microcode Sequencer

IB Register Control

Barrel Shifter

Byte Operations and Flags

2

Temporary Registers (T0 - T7)

Microcode Flags

Multiply

Divide

3

Interrupt Unit- MK, Pl, FT

Enable/Disable Interrupts

4

Status Word Control

User Flags

General Registers (R0 - R15)

5

Timer A

Timer B

-

BIT Pass/Fail Overhead

BIT Fail Codes (FT 13,14,15)

100

101

111

110

111

-

Note: BIT pass is indicated by all zeros in FT bits 13,14, and 15.

Table 4: Built-in Test Coverage and Tuning

Cycles

220

165

216

155

775

25

13/55

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