General Description
The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.

Features
• 36 MHz, general purpose PLL
• 8 FSC timing. (Use the EL4584 for 4 FSC)
• Compatible with EL4583C Sync Separator
• VCXO, Xtal, or LC tank oscillator
• k2nS jitter (VCXO)
• User-controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed popular TV scan rate clock divisors
• Single 5V, low current operation

Applications
• Pixel Clock regeneration
• Video compression engine (MPEG) clock generator
• Video Capture or digitization
• PIP (Picture In Picture) timing generator
• Text or Graphics overlay timing

Description:

The NTE955 series timing Circuit is a highly stable controller capable of producing accurate time de lays, or oscillation. Additional terminals are provided for triggering or resetting if desired. In time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The Circuit may be triggered and reset on falling wave forms, and the output structure can source or sink up to 200mA or drive TTL Circuits.

Features:

Direct Replacement for 555 Timers


Timing from Microseconds through Hours


Operates in Both Astable and Monostable Modes


Adjustable Duty Cycle


High Current Output Can Source or Sink 200mA


Output and Supply TTL Compatible TTL


Temperature Stability of 0.005% per °C


Normally “ON” or Normally “OFF” Output


Available in Three Types:

  NTE955M – 8–Lead DIP

  NTE955S – 8–Lead SIP

  NTE955SM – SOIC–8 (Surface Mount)

Applications:


Precision Timing


Pulse Generation


Sequential Timing


Time Delay Generation


Pulse Width Modulation


Pulse Position Modulation


Linear Ramp Generator

Description:

The NTE955 series timing Circuit is a highly stable controller capable of producing accurate time de lays, or oscillation. Additional terminals are provided for triggering or resetting if desired. In time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The Circuit may be triggered and reset on falling wave forms, and the output structure can source or sink up to 200mA or drive TTL Circuits.

Features:

Direct Replacement for 555 Timers


Timing from Microseconds through Hours


Operates in Both Astable and Monostable Modes


Adjustable Duty Cycle


High Current Output Can Source or Sink 200mA


Output and Supply TTL Compatible TTL


Temperature Stability of 0.005% per °C


Normally “ON” or Normally “OFF” Output


Available in Three Types:

  NTE955M – 8–Lead DIP

  NTE955S – 8–Lead SIP

  NTE955SM – SOIC–8 (Surface Mount)

Applications:


Precision Timing


Pulse Generation


Sequential Timing


Time Delay Generation


Pulse Width Modulation


Pulse Position Modulation


Linear Ramp Generator

General Description
The EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.

Features
• 36 MHz, general purpose PLL
• 4 FSC based timing (use the EL4585 for 8 FSC)
• Compatible w/EL4583 Sync Separator
• VCXO, Xtal, or LC tank oscillator
• < 2 ns jitter (VCXO)
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation

Applications
• Pixel Clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing

General Description
The EL4584C is a PLL (Phase Lock Loop) sub system, designed for video applications but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.

Features
• 36 MHz, general purpose PLL
• 4 FSC based timing (use the EL4585 for 8 FSC)
• Compatible w/EL4583 Sync Separator
• VCXO, Xtal, or LC tank oscillator
• < 2 ns jitter (VCXO)
• User controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed TV scan rate clock divisors
• Selectable external divide for custom ratios
• Single 5V, low current operation

Applications
• Pixel Clock regeneration
• Video compression engine (MPEG) clock generator
• Video capture or digitization
• PIP (Picture in Picture) timing generator
• Text or graphics overlay timing

General Description
The EL4585C is a PLL (Phase Lock Loop) sub system, designed for video applications, but also suitable for general purpose use up to 36 MHz. In a video application this device generates a TTL/CMOS compatible Pixel Clock (Clk Out) which is a multiple of the TV Horizontal scan rate, and phase locked to it.

Features
• 36 MHz, general purpose PLL
• 8 FSC timing. (Use the EL4584 for 4 FSC)
• Compatible with EL4583C Sync Separator
• VCXO, Xtal, or LC tank oscillator
• k2nS jitter (VCXO)
• User-controlled PLL capture and lock
• Compatible with NTSC and PAL TV formats
• 8 pre-programmed popular TV scan rate clock divisors
• Single 5V, low current operation

Applications
• Pixel Clock regeneration
• Video compression engine (MPEG) clock generator
• Video Capture or digitization
• PIP (Picture In Picture) timing generator
• Text or Graphics overlay timing

[TROMPETER]

RED INDICATES Original