HMP8156 データシートの表示（PDF） - Intersil

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HMP8156

NTSC/PAL Encoder

Intersil 

HMP8156

is latched when the Y input data is latched. The pixel and

overlay input timing is shown in Figure 1.

As inputs, BLANK, HSYNC, and VSYNC are latched on

each rising edge of CLK2. As outputs, BLANK, HSYNC, and

VSYNC are output following the rising edge of CLK2. If the

CLK pin is configured as an input, it is ignored. If configured

as an output, it is one-half the CLK2 frequency

8-Bit YCbCr Format with 2X Upscaling

When 8-bit YCbCr format is selected, the data is latched on

the rising edge of CLK2 while CLK is low. The pixel data

must be [Cb Y Cr Y’ Cb Y Cr Y’. . . ], with the first active data

each scan line being Cb data. Overlay data is latched on the

rising edge of CLK2 that latches Y pixel input data. The pixel

and overlay input timing is shown in Figure 2.

As inputs, BLANK, HSYNC, and VSYNC are latched on the

rising edge of CLK2 while CLK is low. As outputs, HSYNC,

VSYNC, and BLANK are output following the rising edge of

CLK2 while CLK is high. In this mode of operation, CLK is

one-half the CLK2 frequency.

CLK2

P8-P15

OL0-OL2,

M1, M0

BLANK

(INPUT)

BLANK

(OUTPUT)

CLK2

Cb 0

Y0

Cr 0

Y1

Cb 2

Y2

PIXEL 0

PIXEL 1

PIXEL 2

YN

PIXEL N

FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITHOUT 2X UPSCALING

CLK

P8-P15

Cb 0

Y0

Cr 0

Y1

Cb 2

Y2

YN

OL0-OL2,

M1, M0

BLANK

(INPUT)

BLANK

(OUTPUT)

PIXEL 0

PIXEL 1

PIXEL 2

PIXEL N

FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats without

2X Upscaling

When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format

is selected without 2X upscaling, the pixel data is latched on

the rising edge of CLK2 while CLK is low. Overlay data is

also latched on the rising edge of CLK2 while CLK is low.

The pixel and overlay input timing is shown in Figures 3 - 5.

As inputs, BLANK, HSYNC, and VSYNC are latched on the

rising edge of CLK2 while CLK is low. As outputs, HSYNC,

VSYNC, and BLANK are output following the rising edge of

CLK2 while CLK is high. In these modes of operation, CLK is

one-half the CLK2 frequency.

16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats with 2X

Upscaling

When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format

is selected and 2X upscaling is enabled, data is latched on

the rising edge of CLK2 while CLK is low. Overlay data is

latched on the rising edge of CLK2 while CLK is low. The

pixel and overlay input timing is shown in Figures 6-8

6

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