MT89L85AP データシートの表示（PDF） - Mitel Networks
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MT89L85AP Datasheet PDF : 20 Pages
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MT89L85
Advance Information
STi3
7
STi4
8
STi5
9
STi6
10
STi7
11
VDD
12
F0i
13
C4i
14
A0
15
A1
16
A2
17
39 STo3
38 STo4
37 STo5
36 STo6
35 STo7
34 VSS
33 D0
32 D1
31 D2
30 D3
29 D4
44 PIN PLCC
VSS
1
DTA 2
STi0 3
STi1 4
STi2 5
NC 6
STi3 7
STi4 8
STi5 9
STi6 10
STi7 11
VDD 12
RESET 13
F0i 14
C4i 15
A0 16
A1 17
A2 18
NC 19
A3 20
A4 21
A5 22
DS 23
R/W 24
48 CSTo
47 ODE
46 STo0
45 STo1
44 STo2
43 NC
42 STo3
41 STo4
40 STo5
39 STo6
38 STo7
37 VSS
36 VDD
35 D0
34 D1
33 D2
32 D3
31 D4
30 NC
29 D5
28 D6
27 D7
26 CS
25 VSS
48 PIN SSOP
(JEDEC MO-118, 300mil Wide)
Pin Description
Figure 2 - Pin Connections
Pin #
44
48
PLCC SSOP
Name
Description
2
3-5
7-11
12
13
14
15-17
19-21
22
2
DTA Data Acknowledgment (Open Drain Output). This active low output indicates that a
data bus transfer is complete. A pull-up resistor is required at this output.
3-5 STi0- ST-BUS Input 0 to 7 (Inputs). Serial data input streams. These streams have 32
7-11 STi7 channels at data rates of 2.048 Mbit/s.
12,36
13
VDD +3.3 Volt Power Supply.
RESET Device Reset (5v-tolerant input). This pin is only available for the 48-pin SSOP
package. This active low input puts the MT89L85 in its reset state. It clears the internal
counters anf registers. All ST-BUS outputs are set to the high impedance state. This
RESET pin must be held low for a minimum of 100nsec to reset the device.
14
F0i Frame Pulse (Input). This input accepts and automatically identifies frame
synchronization signals formatted according to different backplane specifications such
as ST-BUS and GCI.
15
C4i Clock (Input). 4.096 MHz serial clock for shifting data in and out of the data streams.
16-18 A0-A5 Address 0 to 5 (Inputs). These lines provide the address to MT89L85 internal
20-22
registers.
23
DS Data Strobe (Input). This is the input for the active high data strobe on the
microprocessor interface. This input operates with CS to enable the internal read and
write generation.
2
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