AD7841 データシートの表示（PDF） - Analog Devices
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AD7841 Datasheet PDF : 13 Pages
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AD7841
AC PERFORMANCE CHARACTERISTICS (These characteristics are included for Design Guidance and are not subject
to production testing.)
Parameter
A&B
Versions Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 31
Slew Rate
0.7
Digital-to-Analog Glitch Impulse 230
Channel-to-Channel Isolation 99
DAC-to-DAC Crosstalk
40
Digital Crosstalk
0.2
Digital Feedthrough
0.1
Output Noise Spectral Density
@ 1 kHz
200
µs typ
V/µs typ
nV-s typ
dB typ
nV-s typ
nV-s typ
nV-s typ
Full-Scale Change to ± 1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
Measured with VREF(+) = +5 V, VREF(–) = –5 V. DAC Latch
Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions
See Terminology
See Terminology
Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Effect of Input Bus Activity on DAC Output Under Test
nV/√Hz typ All 1s Loaded to DAC. VREF(+) = VREF(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS1, 2 (VCC = 5 V ؎ 5%; VDD = 15 V ؎ 10%; VSS = –15 V ؎ 10%; GND = DUTGND = 0 V)
Parameter
Limit at TMIN, TMAX
Unit
t1
15
t2
0
t3
50
t4
50
t5
0
t6
0
t7
20
t8
0
t9
31
t10
300
t11
50
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs typ
ns max
ns min
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
Description
Address to WR Setup Time
Address to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
CS to WR Setup Time
WR to CS Hold Time
Data Setup Time
Data Hold Time
Settling Time
CLR Pulse Activation Time
LDAC Pulsewidth Low
A0, A1, A2
CS
WR
DATA
VOUT
CLR
t1
t2
t5
t6
t3
t4
t7
t8
t9
t10
VOUT
LDAC
t11
Figure 1. Timing Diagram
REV. B
–3–
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