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74LV245PW(2016) データシートの表示(PDF) - NXP Semiconductors.

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74LV245PW
(Rev.:2016)
NXP
NXP Semiconductors. NXP
74LV245PW Datasheet PDF : 15 Pages
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74LV245
Octal bus transceiver; 3-state
Rev. 4 — 9 March 2016
Product data sheet
1. General description
The 74LV245 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC245 and 74HCT245.
The 74LV245 is an octal transceiver with non-inverting 3-state bus compatible outputs in
both send and receive directions. A send/receive (DIR) input controls direction, and an
output enable (OE) input makes easy cascading possible. Pin OE controls the outputs so
that the buses are effectively isolated.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74LV245D
40 C to +125 C SO20
74LV245DB
40 C to +125 C SSOP20
74LV245PW
40 C to +125 C TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
Version
SOT163-1
SOT339-1
SOT360-1

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