SN74LS377DWR2 データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

SN74LS377DWR2

Octal D Flip-Flop with Enable

ON Semiconductor 

SN74LS377

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

VIH

Parameter

Input HIGH Voltage

Min Typ Max Unit

Test Conditions

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

VIK

VOH

Input Clamp Diode Voltage

Output HIGH Voltage

–0.65 –1.5

V

VCC = MIN, IIN = –18 mA

2.7

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOL

Output LOW Voltage

0.25 0.4

0.35 0.5

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN = VIL or VIH

V

IOL = 8.0 mA

per Truth Table

IIH

Input HIGH Current

20

µA VCC = MAX, VIN = 2.7 V

0.1

mA VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

–0.4 mA VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1.)

–20

–100 mA VCC = MAX

ICC

Power Supply Current

28

mA VCC = MAX, NOTE 1

NOTE: With all inputs open and GND applied to all data and enable inputs, ICC is measured after a momentary GND, then 4.5 V is applied to clock.

1. Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max

fMAX

Maximum Clock Frequency

30

40

tPLH

tPHL

Propagation Delay,

Clock to Output

17

27

18

27

Unit

MHz

ns

Test Conditions

VCC = 5.0 V

CL = 15 pF

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min

Typ

Max

Unit

tW

Any Pulse Width

20

ns

ts

Data Setup Time

20

ns

Enable Setup

Inactive — State

10

ns

ts

Time

Active — State

25

ns

th

Any Hold Time

5.0

ns

Test Conditions

VCC = 5.0 V

DEFINITION OF TERMS

SETUP TIME (ts) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW-to-HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW-to-HIGH that the

logic level must be maintained at the input in order to ensure

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW-to-HIGH and still be recognized.

http://onsemi.com

3

Share Link: