74LVC543AD データシートの表示（PDF） - Philips Electronics

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74LVC543AD

Octal D-type registered transceiver (3-State)

Philips Electronics 

Philips Semiconductors

Octal D-type registered transceiver (3-State)

Product specification

74LVC543A

FEATURES

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

• Supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8–1A

• CMOS low power consumption

• Direct interface with TTL levels

• 8-bit octal transceiver with D-type latch

• Back-to-back registers for storage

• Separate controls for data flow in each direction

• 3-State non-inverting outputs for bus oriented applications

• High impedance when VCC = 0V

DESCRIPTION

The 74LVC543A is a high–performance, low–power, low–voltage,

Si–gate CMOS device and superior to most advanced CMOS

compatible TTL families.

The 74LVC543A is an octal registered transceiver containing two

sets of D–type latches for temporary storage of the data flow in

either direction. Separate latch enable (LEAB, LEBA) and output

enable (OEAB, OEBA) inputs are provided for each register to permit

independent control of inputting and outputting in either direction of

the data flow.

The 74LVC543A contains eight D–type latches, with separate inputs

and controls for each set. For data flow from A to B, for example, the

A–to–B enable (EAB) input must be LOW in order to enter data from

A0–A7 or take data from B0–B7, as indicated in the function table.

With EAB LOW, a LOW signal on the A–to–B latch enable (LEAB)

input makes the A–to–B latches transparent; a subsequent LOW–to

HIGH transition of the LEAB signal puts the A data into the latches

where it is stored and the B outputs no longer change with the A

inputs. With EAB and OEAB both low, the 3–state B output buffers

are active and display the data present at the outputs of the A

latches

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; Tr = Tf ≤ 2.5ns

SYMBOL

PARAMETER

tPHL/tPLH

Propagation delay

An to Bn

CI

input capacitance

CI/O

input/output capacitance

CPD

power dissipation capacitance per latch

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD x VCC2 x fi +Σ (CL x VCC2 x fo ) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

Σ (CL x VCC2 x fo ) = sum of the outputs

2. The condition is VI = GND to VCC

CONDITIONS

CL = 50 pF

VCC = 3.3V

VCC = 3.3V

ORDERING INFORMATION

PACKAGES

24-Pin Plastic Small Outline (SO)

24-Pin Plastic Shrink Small Outline (SSOP) Type II

24-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I

TEMPERATURE

RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH

AMERICA

74LVC543A D

74LVC543A DB

74LVC543A PW

TYPICAL

3.3

5.0

10.0

27

UNIT

ns

pF

pF

pF

NORTH AMERICA

74LVC543A D

74LVC543A DB

7LVC543APW DH

PKG DWG. #

SOT137-1

SOT340-1

SOT355-1

1998 Jul 31

2

853-1992 19813

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