AD7228 データシートの表示（PDF） - Analog Devices
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AD7228 Datasheet PDF : 15 Pages
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AD7228
Data Sheet
SINGLE SUPPLY
VDD = 15 V ± 10%, VSS = GND, GND = 0 V, VREF = 10 V, RL = 2 kΩ, CL = 100 pF, unless otherwise noted. All specifications TMIN to TMAX,
−40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
Total Unadjusted Error1
Differential Nonlinearity
Minimum Load Resistance
REFERENCE INPUT
Input Resistance
Input Capacitance2
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance2
Input Coding
DYNAMIC PERFORMANCE2
Voltage Output Slew Rate
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
Digital Crosstalk3
POWER SUPPLIES
VDD Range
IDD
at 25°C
TMIN to TMAX
K and B L and C
Versions Versions Unit
Test Conditions/Comments
8
8
Bits
±2
±1
LSB max
±1
±1
LSB max
Guaranteed monotonic
2
2
kΩ min
VOUT = 10 V
2
2
kΩ min
500
500
pF max
Occurs when each DAC is loaded with all 1s
2.4
0.8
±1
8
Binary
2.4
0.8
±1
8
Binary
V min
V max
µA max
pF max
VIN = 0 V or VDD
2
2
V/µs min
5
5
µs max
Settling time to ±1/2 LSB
7
7
µs max
Settling time to ±1/2 LSB
50
50
nV-sec typ
Code transition all 0s to all 1s, VREF = 0 V, WR = VDD
50
50
nV-sec typ
Code transition all 0s to all 1s, VREF = 10 V, WR = 0 V
13.5/16.5
16
20
13.5/16.5
16
20
V min/V max
mA max
mA max
For specified performance
Outputs unloaded; VIN = VINL or VINH
1 Total unadjusted error includes zero code error, relative accuracy and full-scale error.
2 Sample tested at TA = 25°C to ensure compliance.
3 The glitch impulse transferred to the output of one converter (not addressed) due to a change in the digital input code to another addressed converter.
Rev. D | Page 4 of 15
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