LC74751 データシートの表示（PDF） - SANYO -> Panasonic
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LC74751 Datasheet PDF : 15 Pages
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LC74751
Memory Organization (display RAM and control RAM)
Both memory addresses and data are 16-bit quantities.
The locations at addresses 000 (000 hexadecimal) to 175 (0AF hexadecimal) hold display memory (RAM) data.
The locations at addresses 176 (0B0 hexadecimal) to 191 (0BF hexadecimal) hold display control register data.
Bit DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA DA
Address
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
000
(000h)
0
0
0
0
0
0
0
0 ATTR C6 C5 C4 C3 C2 C1 C0
Notes
ATTR
Character code
Display RAM
175
(0AFh)
0
0
0
0
0
0
0
0 ATTR C6 C5 C4 C3 C2 C1 C0
176
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B0h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the first line
177
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B1h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the second line
178
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B2h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the third line
179
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B3h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the fourth line
180
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B4h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the fifth line
181
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B5h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the sixth line
182
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B6h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the seventh line
183
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B7h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the eighth line
184
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B8h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the ninth line
185
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0B9h)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the tenth line
186
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0BAh)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the eleventh line
187
ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR ADR Display line ROM specification
(0BBh)
0
0
0
0
0
A
9
8
7
6
5
4
3
2
1
0 First character in the twelfth line
188
HSZ HSZ HSZ HSZ HSZ HSZ
Horizontal display position
(0BCh)
0
0
0
0
31
30
21
20
11
10 HP5 HP4 HP3 HP2 HP1 HP0 Horizontal character size
189
VSZ VSZ VSZ VSZ VSZ VSZ
Vertical display position
(0BDh)
0
0
0
0
31
30
21
20
11
10 VP5 VP4 VP3 VP2 VP1 VP0 Vertical character size
190
INT/ LC/ 2fsc/ OSC DSP
SYS SIG SIG PHASE PHASE PHASE
(0BEh)
0
0
0
0
NON XTAL 4fsc STP ON MUTE RST MD1 MD0
2
1
0 Video signal and other items
191
TST VSN
BLK BLK RVS BLINK BLINK BLINK EXT/
(0BFh)
0
0
0
0 MOD SEP
0
1
0
ON
2
1
0
INT CBOFF BCOL Control register
No. 5396-6/15
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