LC74751 データシートの表示（PDF） - SANYO -> Panasonic

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LC74751

On-Screen Display LSI

SANYO -> Panasonic 

LC74751

Address 190 (0BE hexadecimal)

DA

Register

0 to C

State

Contents

Function

0

0

PHASE0

1

0

1

PHASE1

1

0

2

PHASE2

1

Background color (phase)

PHASE2 PHASE1 PHASE0

NTSC

PAL (PAL-M, N)

0

0

0

π/2

± π/2

0

0

1

π

In phase

0

1

0

3π/2

+- π/2

0

1

1 In phase

±π

1

0

0

π/4

±3π/4

1

0

1

3π/4

±π/4

1

1

0

5π/4

+- π/4

1

1

1

7π/4

±3π/4

0

3

SIGMD0

1

0

4

SIGMD1

1

SIGMD1

0

0

1

1

SIGMD0

0

1

0

1

Signal format

NTSC

PAL

PAL-M

PAL-N

0

5

SYSRST

1 Resets all registers and turns display off.

0 Normal output

6

MUTE

1 CVIN is cut and CVOUT is fixed at the pedestal level.

0 Character display off

7

DSPON

1 Character display on

0 Crystal oscillator and LC oscillator circuits are not stopped.

8 OSCSTP

1 Stops the crystal oscillator and LC oscillator circuits.

2fsc/

0 Clock frequency: 2fsc

9

4fsc/

1 Clock frequency: 4fsc

LC/

0 The LC oscillator is used for the dot clock.

A

XTAL

1 The crystal oscillator is used for the dot clock.

INT/

0

Interlaced (262.5 H per field: NTSC, 312.5 H per field: PAL)

B

NON

1 Noninterlaced (263 H per field: NTSC, 313 H per field: PAL)

Note: The states of all registers are set to zero when the IC is reset by the RST pin.

Notes

Background color

The phase of the background color with

respect to the color burst signal.

The IC is reset by a low level on the CS pin, and the

reset state is cleared by a high level on that pin.

Only valid in external synchronization mode

when character display is off.

Crystal oscillator circuit frequency

The OSCIN pin must be tied to VDD if the LC

oscillator circuit is not used.

Switches interlaced and noninterlaced display.

No. 5396-9/15

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