ORT82G5 データシートの表示（PDF） - Agere -> LSI Corporation

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ORT82G5

ORCA® ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC

Agere -> LSI Corporation 

Preliminary Data Sheet

July 2001

ORCA ORT82G5 FPSC Eight-Channel

1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface

System-Level Features (continued)

Configuration

The FPGAs functionality is determined by internal con-

figuration RAM. The FPGAs internal initialization/con-

figuration circuitry loads the configuration data at

powerup or under system control. The configuration

data can reside externally in an EEPROM or any other

storage media. Serial EEPROMs provide a simple, low

pin-count method for configuring FPGAs.

The RAM is loaded by using one of several configura-

tion modes. Supporting the traditional master/slave

serial, master/slave parallel, and asynchronous periph-

eral modes, the Series 4 also utilizes its microproces-

sor interface and embedded system bus to perform

both programming and readback. Daisy chaining of

multiple devices and partial reconfiguration are also

permitted.

Other configuration options include the initialization of

the embedded-block RAM memories and FPSC mem-

ory as well as system bus options and bit stream error

checking. Programming and readback through the

JTAG (IEEE 1149.2) port is also available meeting in-

system programming (ISP) standards (IEEE 1532

Draft).

Additional Information

Contact your local Agere representative for additional

information regarding the ORCA Series 4 FPGA

devices, or visit our website at:

http://www.agere.com/orca

ORT82G5 Overview

Device Layout

The ORT82G5 is a backplane transceiver FPSC with

embedded CDR and SERDES circuitry and 8b/10b

encoding/decoding. It is intended for high-speed serial

backplane data transmission. Built using Series 4

reconfigurable system-on-chips (SoC) architecture, it

also contains up to 400k usable FPGA system gates.

The ORT82G5 contains an FPGA base array, an eight-

channel clock and data recovery macro, and an eight-

channel 8b/10b interface on a single monolithic chip.

version II of this device, which will be plug-in compati-

ble to version I, also adds SONET scrambling capabil-

ity. The version II features are not described in this data

sheet. Figure 1 shows the ORT82G5 block diagram.

Boundary scan for the ORT82G5 only includes pro-

grammable I/Os and does not include any of the

embedded block I/Os.

Backplane Transceiver Interface

The ORT82G5 backplane transceiver FPSC has eight

channels, each operating at up to 3.125 Gbits/s

(2.5 Gbits/s data rate) with a full-duplex synchronous

interface with built-in clock recovery (CDR). The CDR

macro with 8b/10b provides guaranteed ones density

for the CDR, byte alignment, and error detection.

The CDR interface provides a physical medium for

high-speed asynchronous serial data transfer between

system devices. Devices can be on the same PC-

board, on separate boards connected across a back-

plane, or connected by cables. This core is intended

for, but not limited to, terminal equipment in SONET/

SDH, Gbit Ethernet, 10 Gbit Ethernet, ATM, fibre-chan-

nel, and Infiniband systems.

The SERDES circuitry consists of receiver, transmitter,

and auxiliary functional blocks. The receiver accepts

high-speed (up to 3.125 Gbits/s) serial data. Based on

data transitions the receiver locks an analog receive

PLL for each channel to retime the data, then demulti-

plexes down to parallel bytes and clock. The transmitter

operates in the reverse direction. Parallel bytes are

multiplexed up to 3.125 Gbits/s serial data for off-chip

communication. The transmitter generates the neces-

sary 3.125 GHz clocks for operation from a lower

speed reference clock.

This device will support 8b/10b encoding/decoding,

which is capable of frame synchronization and physical

link monitoring. Figure 2 shows the internal architec-

ture of the ORT82G5 backplane transceiver core.

Agere Systems Inc.

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