ORT82G5 データシートの表示（PDF） - Agere -> LSI Corporation

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ORT82G5

ORCA® ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC

Agere -> LSI Corporation 

ORCA ORT82G5 FPSC Eight-Channel

1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface

Preliminary Data Sheet

July 2001

Description (continued)

Following design entry, the development system’s map,

place, and route tools translate the netlist into a routed

FPGA. A floorplanner is available for layout feedback

and control. A static timing analysis tool is provided to

determine device speed and a back-annotated netlist

can be created to allow simulation and timing.

Timing and simulation output files from ORCA Foundry

are also compatible with many third-party analysis

tools. Its bit stream generator is then used to generate

the configuration data which is loaded into the FPGAs

internal configuration RAM, embedded block RAM,

and/or FPSC memory.

When using the bit stream generator, the user selects

options that affect the functionality of the FPGA. Com-

bined with the front-end tools, ORCA Foundry pro-

duces configuration data that implements the various

logic and routing options discussed in this data sheet.

FPSC Design Kit

Development is facilitated by an FPSC design kit

which, together with ORCA Foundry and third-party

synthesis and simulation engines, provides all software

and documentation required to design and verify an

FPSC implementation. Included in the kit are the FPSC

configuration manager, Synopsys Smart Model ®, and

complete online documentation. The kit's software cou-

ples with ORCA Foundry, providing a seamless FPSC

design environment. More information can be obtained

by visiting the ORCA website or contacting a local

sales office, both listed on the last page of this docu-

ment.

FPGA Logic Overview

The ORCA Series 4 architecture is a new generation of

SRAM-based programmable devices from Agere. It

includes enhancements and innovations geared toward

today’s high-speed systems on a single chip. Designed

with networking applications in mind, the Series 4 fam-

ily incorporates system-level features that can further

reduce logic requirements and increase system speed.

ORCA Series 4 devices contain many new patented

enhancements and are offered in a variety of packages

and speed grades.

The hierarchical architecture of the logic, clocks, rout-

ing, RAM, and system-level blocks create a seamless

merge of FPGA and ASIC designs. Modular hardware

and software technologies enable system-on-chip inte-

gration with true plug-and-play design implementation.

The architecture consists of four basic elements: pro-

grammable logic cells (PLCs), programmable I/O cells

(PIOs), embedded block RAMs (EBRs), and system-

level features. These elements are interconnected with

a rich routing fabric of both global and local wires. An

array of PLCs are surrounded by common interface

blocks which provide an abundant interface to the adja-

cent PLCs or system blocks. Routing congestion

around these critical blocks is eliminated by the use of

the same routing fabric implemented within the pro-

grammable logic core. Each PLC contains a PFU,

SLIC, local routing resources, and configuration RAM.

Most of the FPGA logic is performed in the PFU, but

decoders, PAL-like functions, and 3-state buffering can

be performed in the SLIC. The PIOs provide device

inputs and outputs and can be used to register signals

and to perform input demultiplexing, output multiplex-

ing, uplink and downlink functions, and other functions

on two output signals. Large blocks of 512 x 18 quad-

port RAM complement the existing distributed PFU

memory. The RAM blocks can be used to implement

RAM, ROM, FIFO, multiplier, and CAM. Some of the

other system-level functions include the MPI, PLLs,

and the embedded system bus (ESB).

PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit)

LUTs, eight latches/FFs, and one additional flip-flop

that may be used independently or with arithmetic func-

tions.

The PFU is organized in a twin-quad fashion; two sets

of four LUTs and FFs that can be controlled indepen-

dently. Each PFU has two independent programmable

clocks, clock enables, local set/reset, and data selects.

LUTs may also be combined for use in arithmetic func-

tions using fast-carry chain logic in either 4-bit or 8-bit

modes. The carry-out of either mode may be registered

in the ninth FF for pipelining. Each PFU may also be

configured as a synchronous 32 x 4 single- or dual-port

RAM or ROM. The FFs (or latches) may obtain input

from LUT outputs or directly from invertible PFU inputs,

or they can be tied high or tied low. The FFs also have

programmable clock polarity, clock enables, and local

set/reset.

8

Agere Systems Inc.

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