SP8854EKGHCAR データシートの表示（PDF） - Mitel Networks

部品番号

コンポーネント説明

メーカー

SP8854EKGHCAR

0.3-6.0V; 2-7GHz synthesiser. For complete 2-7GHz single chip system

Mitel Networks 

Supersedes January 1996 version, DS4238 - 1.2

SP8854E

2·7GHz Parallel Load Professional Synthesiser

Preliminary Information

DS4238 - 2.0 June 1998

The SP8854E is one of a family of parallel load synthesisers

containing all the elements apart from the loop amplifier to

fabricate a PLL synthesis loop. Other parts in the series are

the SP8852E which is fully programmable, requiring tw0 16-

bit words to set the RF and reference counters and the

SP8855E which is fully programmable using hard wired links

or switches.

The SP8854E is programmed using a 16-bit parallel data

bus. Data is stored in an internal buffer. The 10-bit program-

mable reference divider is programmed by connecting the 10

programming pins either to ground or 15V. The device can

therefore be programmed with a single transfer from the

control microprocessor. Hard wired inputs can also control

the FPD and FREF outputs and the control sense of the loop.

FEATURES

s 2·7 GHz Operating Frequency

s Single 5V Supply

s Low Power Consumption <1·3W

s High Comparison Frequency : 20MHz

s High Gain Phase Detector : 1mA/rad

s Zero ‘Dead Band’ Phase Detector

s Wide Range of RF and Reference Division Ratios

s Programming by Single Word Data Transfer

ABSOLUTE MAXIMUM RATINGS

Supply voltage

Operating temperature

Storage temperature

Prescaler and reference input voltage

Data inputs

Junction temperature

20·3V to 16V

255°C to1100°C

265°C to 1150°C

2·5V p-p

VCC 10·3V

VEE 20·3V

1175°C

ORDERING INFORMATION

SP8854E KG HCAR Non-standard temperature range,

255°C to 1100°C, standard product screening

SP8854E IG HCAR Industrial temperature range,

240°C to 185°C, standard product screening

DATA BIT 4

DATA BIT 3

DATA BIT 2

DATA BIT 1

DATA BIT 0

0V (PRESCALER)

RF INPUT

RF INPUT

VCC (PRESCALER)

VEE

LOCK DETECT

1 44

SP8854E

STROBE

REF DIV BIT 0

REF DIV BIT 1

REF DIV BIT 2

REF DIV BIT 3

REF DIV BIT 4

REF DIV BIT 5

REF DIV BIT 6

REF DIV BIT 7

REF DIV BIT 8

REF DIV BIT 9

HC44

*FPD and FREF outputs are reversed using the control

direction input, pin 23. The above diagram is correct

when pin 23 is high.

Fig. 1 Pin connections - top view

THERMAL DATA

uJC = 5°C/W

uJA = 53°C/W

ESD PROTECTION

1000V, human body model

Share Link: