HT9480(1998) データシートの表示（PDF） - Holtek Semiconductor
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HT9480 Datasheet PDF : 57 Pages
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HT9480
System Architecture
Execution flow
The HT9480 system clock can be derived from
either a crystal or an RC oscillator. It is inter-
nally divided into four non-overlapping clocks
denoted by P1, P2, P3, and P4. Each instruction
cycle consists of T1 to T4.
Instruction fetching and execution are pipe-
lined in such a way that a fetch takes an in-
struction cycle while decoding and execution
take the next instruction cycle. The pipelining
scheme causes each instruction to effectively
execute within a cycle. If an instruction changes
the content of the program counter two cycles
are required to complete the instruction.
Program counter – PC
The program counter (PC) is 13-bit wide and
controls the program ROM instruction se-
quence execution. The contents of the PC can
specify a of maximum 8192 addresses.
Execution flow
Mode
Program Counter
*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial reset
0 0 0000000000 0
Data ready interrupt and
battery fail interrupt
0
0
0
000000010
0
Programmable timer
interrupt
0 0 0000000100 0
Timer/event Counter
interrupt
0 0 0000000110 0
Skip
PC+2
Loading PCL
*12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, call branch
#12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program counter
Notes:
*12~*0: Program counter bits
#12~#0: Instruction code bits
S12~S0: Stack register bits
@7~@0: PCL bits
7
23th Feb ’98
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