AD1848 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD1848 Datasheet PDF : 28 Pages
| |||
AD1848K
PIN DESCRIPTION
Parallel Interface
Pin Name PLCC
CDRQ
12
CDAK
11
PDRQ
14
PDAK
ADR1:0
13
9 & 10
RD
60
WR
61
CS
59
DATA7:0
DBEN
3–6 &
65–68
63
DBDIR
62
TQFP I/O
3
O
2
I
5
O
4
I
1 & 64 I
47
I
48
I
46
I
52–55 & I/O
58–61
50
O
49
O
Description
Capture Data Request. The assertion of this signal indicates that the Codec has a cap-
tured audio sample from the ADC ready for transfer. This signal will remain asserted un-
til all the bytes from the capture buffer have been transferred.
Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
Playback Data Request. The assertion of this signal indicates that the Codec is ready for
more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.
Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
Codec Addresses. These address pins are asserted by the Codec interface logic during a
control register/PIO access. The state of these address lines determine which register is
accessed.
Read Command Strobe. This active LO signal defines a read cycle from the Codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.
Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the
Codec’s DMA sample registers.
AD1848K Chip Select. The Codec will not respond to any control/PIO cycle accesses
unless this active LO signal is LO. This signal is ignored during DMA transfers.
Data Bus. These pins transfer data and control information between the Codec and the
host.
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN = (WR or RD) and CS
For DMA cycles,
DBEN = (WR or RD) and (PDAK or CDAK)
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI
enables writes from the host to the AD1848K; LO enables reads from the AD1848K to
the host bus. This signal is normally HI.
For control register/PIO cycles,
DBDIR = RD and CS
For DMA cycles,
DBDIR = RD and (PDAK or CDAK)
REV. 0
–7–
Share Link: 