2SJ448 データシートの表示（PDF） - NEC => Renesas Technology

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2SJ448

SWITCHING P-CHANNEL POWER MOS FET

NEC => Renesas Technology 

2SJ448

ELECTRICAL CHARACTERISTICS (TA = 25°C)

Characteristics

Symbol

Test Conditions

Zero Gate Voltage Drain Current

Gate Leakage Current

Gate Cut-off Voltage

Forward Transfer Admittance

Drain to Source On-state Resistance

Input Capacitance

IDSS

IGSS

VGS(off)

| yfs |

RDS(on)

Ciss

VDS = –250 V, VGS = 0 V

VGS = m 25 V, VDS = 0 V

VDS = –10 V, ID = –1 mA

VDS = –10 V, ID = –2.0 A

VGS = –10 V, ID = –2.0 A

VDS = –10 V

Output Capacitance

Coss

VGS = 0 V

Reverse Transfer Capacitance

Crss

f = 1 MHz

Turn-on Delay Time

td(on) VDD = –125 V, ID = –2.0 A

Rise Time

tr

VGS = –10 V

Turn-off Delay Time

td(off)

RG = 10 Ω

Fall Time

tf

Total Gate Charge

QG

VDD= –200 V

Gate to Source Charge

QGS

VGS = –10 V

Gate to Drain Charge

QGD ID = –4.0 A

Body Diode Forward Voltage

VF(S-D) IF = 4.0 A, VGS = 0 V

Reverse Recovery Time

trr

IF = 4.0 A, VGS = 0 V

Reverse Recovery Charge

Qrr

di/dt = 50 A / µs

MIN. TYP. MAX. Unit

–100 µA

m 10 µA

–4.0 –4.8 –5.5

V

1.0 2.3

S

1.5 2.0

Ω

470

pF

200

pF

70

pF

13

ns

7

ns

34

ns

10

ns

15

nC

4

nC

9

nC

1.0

V

195

ns

760

nC

TEST CIRCUIT 1 AVALANCHE CAPABILITY

TEST CIRCUIT 2 SWITCHING TIME

D.U.T.

RG = 25 Ω

L

PG.

50 Ω

VDD

VGS = –20 → 0 V

ID

VDD

IAS BVDSS

VDS

Starting Tch

TEST CIRCUIT 3 GATE CHARGE

D.U.T.

IG = –2 mA

RL

PG.

50 Ω

VDD

D.U.T.

RG

PG.

RG = 10 Ω

VGS

0

τ

τ = 1 µs

Duty Cycle ≤ 1%

RL VGS VGS(−)

Wave 0 10%

Form

VDD

ID(−)

VGS

90%

ID

Wave

Form

10%

0

td (on)

ID

t t r

d (off)

90%

90%

10%

tf

ton

toff

2

Data Sheet D10029EJ2V0DS

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