T8110-BAL-DB データシートの表示（PDF） - Agere -> LSI Corporation
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T8110-BAL-DB
Agere -> LSI Corporation
T8110-BAL-DB Datasheet PDF : 222 Pages
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Ambassador T8110 PCI-Based H.100/H.110 Switch
and Packet Payload Engine
Data Sheet
May 2001
Contents
Table of Contents (continued)
Page
7.7.1 Clock Fallback ................................................................................................................................. 82
7.7.1.1 Fallback Events ................................................................................................................... 82
7.7.1.2 Fallback Scenarios—Fixed vs. Rotating Secondary ............................................................ 83
7.7.1.3 H-Bus Clock Enable/Disable on Fallback ............................................................................ 86
7.7.2 Clock Failsafe ..................................................................................................................................88
7.7.2.1 Failsafe Events ....................................................................................................................88
8 Frame Group and FG I/O .................................................................................................................................... 90
8.1 Frame Group Control Registers ....................................................................................................................90
8.1.1 FGx Lower and Upper Start Registers ............................................................................................. 90
8.1.2 FGx Width Registers ........................................................................................................................ 91
8.1.3 FGx Rate Registers ......................................................................................................................... 91
8.2 FG7 Timer Option ......................................................................................................................................... 92
8.2.1 FG7 Counter (Low and High Byte) Registers .................................................................................. 92
8.3 FGIO Control Registers ................................................................................................................................ 93
8.3.1 FGIO Data Register ......................................................................................................................... 93
8.3.2 FGIO Read Mask Register .............................................................................................................. 93
8.3.3 FGIO R/W Register .......................................................................................................................... 94
8.4 FG Circuit Operation ..................................................................................................................................... 95
8.4.1 Frame Group 8 kHz Reference Generation .....................................................................................96
8.4.2 FGIO General-Purpose Bits ............................................................................................................. 97
8.4.3 Programmable Timer (FG7 Only) .................................................................................................... 97
8.4.4 FG External Interrupts ..................................................................................................................... 97
8.4.5 FG Diagnostic Test Point Observation ............................................................................................97
9 General-Purpose I/O ........................................................................................................................................... 98
9.1 GPIO Control Registers ................................................................................................................................ 98
9.1.1 GPIO Data Register ......................................................................................................................... 98
9.1.2 GPIO Read Mask Register .............................................................................................................. 99
9.1.3 GPIO R/W Register ......................................................................................................................... 99
9.1.4 GPIO Override Register ................................................................................................................. 100
9.2 GP Circuit Operation ................................................................................................................................... 100
9.2.1 GPIO General-Purpose Bits .......................................................................................................... 101
9.2.2 GP Dual-Purpose Bits GPIO (Override) ......................................................................................... 101
9.2.2.1 GP H.110 Clock Master Indicators (GP0, GP1 Only) ........................................................ 101
9.2.2.2 PCI_RST# Indicator (GP2 Only) ........................................................................................101
9.2.3 GP External Interrupts ................................................................................................................... 101
9.2.4 GP Diagnostic Test Point Observation ..........................................................................................101
10 Stream Rate Control ....................................................................................................................................... 102
10.1 H-Bus Stream Rate Control Registers ................................................................................................... 103
10.1.1 H-Bus Rate Registers ....................................................................................................................103
10.2 L-Bus Stream Rate Control Registers ................................................................................................... 103
10.2.1 L-Bus Rate Registers ..................................................................................................................... 103
10.2.2 L-Bus 16.384 Mbits/s Operation .................................................................................................... 104
10.2.3 16.384 Mbits/s Local I/O Superrate ...............................................................................................105
11 Minibridge ........................................................................................................................................................107
11.1 Wait-State Control Registers ................................................................................................................. 107
11.1.1 Minibridge Wait-State Control Registers ........................................................................................107
11.2 Strobe Control Registers ....................................................................................................................... 110
11.3 Minibridge Circuit Operation ..................................................................................................................110
11.4 Minibridge Operational Addressing ....................................................................................................... 112
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