QL3012-0PL84C(1999) データシートの表示（PDF） - QuickLogic Corporation

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QL3012-0PL84C
(Rev.:1999)

12,000 Usable PLD Gate pASIC®3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

QL3012

Pin

TDI

TRSTB

TMS

TCK

TDO

STM

I/ACLK

I/GCLK

I

I/O

VCC

VCCIO

GND

PIN DESCRIPTIONS

Function

Test Data In for JTAG

Active low Reset for JTAG

Test Mode Select for JTAG

Test Clock for JTAG

Test data out for JTAG

Special Test Mode

High-drive input and/or

array network driver

High-drive input and/or

global network driver

High-drive input

Input/Output pin

Power supply pin

Input voltage tolerance pin

Ground pin

Description

Hold HIGH during normal operation. Connect to

VCC if not used for JTAG.

Hold LOW during normal operation. Connect to

ground if not used for JTAG.

Hold HIGH during normal operation. Connect to

VCC if not used for JTAG.

Hold HIGH or LOW during normal operation.

Connect to VCC or ground if not used for JTAG.

Output that must be left unconnected if not used

for JTAG.

Must be grounded during normal operation.

Can be configured as either or both.

Can be configured as either or both.

Use for input signals with high fanout.

Can be configured as an input and/or output.

Connect to 3.3V supply.

Connect to 5.0 volt supply if 5 volt input tolerance

is required, otherwise connect to 3.3V supply.

Connect to ground.

4

pASIC 3

QuickLogic

pASIC device

pASIC 3 device

part number

QL 3012 - 1 PF144 C

Operating Range

C = Commercial

I = Industrial

*M = Military

ORDERING

INFORMATION

Speed Grade

0 = quick

1 = fast

2 = faster

3 = faster

*4 = fastest

Package Code

PL84 = 84-pin PLCC

PF100 = 100-pin TQFP

PF144 = 144-pin TQFP

* Contact QuickLogic regarding availability.

4-29

QL3012-rev. B

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