AD9762 データシートの表示（PDF） - Analog Devices

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AD9762

12-Bit, 125 MSPS TxDAC® D/A Converter

Analog Devices 

AD9762

REFERENCE OPERATION

The AD9762 contains an internal 1.20 V bandgap reference

that can be easily disabled and overridden by an external refer-

ence. REFIO serves as either an input or output depending on

whether the internal or an external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 40, the internal

reference is activated and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1 µF or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external

amplifier having an input bias current less than 100 nA if any

additional loading is required.

OPTIONAL

EXTERNAL

REF BUFFER

ADDITIONAL

LOAD

0.1␮F

2k⍀

REFLO

+1.2V REF

REFIO

FS ADJ

AD9762

+5V

0.1␮F

COMP1 AVDD

50pF

CURRENT

SOURCE

ARRAY

The control amplifier allows a wide (10:1) adjustment span of

IOUTFS over a 2 mA to 20 mA range by setting IREF between

62.5 µA and 625 µA. The wide adjustment span of IOUTFS

provides several application benefits. The first benefit relates

directly to the power dissipation of the AD9762, which is

proportional to IOUTFS (refer to the Power Dissipation section).

The second benefit relates to the 20 dB adjustment, which is

useful for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 1.4 MHz and can be reduced by connecting an

external capacitor between COMP1 and AVDD. The output of

the control amplifier, COMP1, is internally compensated via a

50 pF capacitor that limits the control amplifier small-signal

bandwidth and reduces its output impedance. Any additional

external capacitance further limits the bandwidth and acts as a

filter to reduce the noise contribution from the reference ampli-

fier. Figure 42 shows the relationship between the external

capacitor and the small signal –3 dB bandwidth of the

1000

Figure 40. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may then be applied

to REFIO as shown in Figure 41. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1 µF compensation capacitor is not required

since the internal reference is disabled, and the high input

impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the

external reference.

AVDD

0.1␮F

AVDD

EXTERNAL

REF

VREFIO

REFLO

+1.2V REF

REFIO

FS ADJ

RSET

IREF =

VREFIO/RSET

AD9762

COMP1 AVDD

50pF

CURRENT

SOURCE

ARRAY

REFERENCE

CONTROL

AMPLIFIER

Figure 41. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9762 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, IOUTFS.

The control amplifier is configured as a V-I converter as shown

in Figure 41, such that its current output, IREF, is determined by

the ratio of the VREFIO and an external resistor, RSET, as stated

in Equation 4. IREF is copied over to the segmented current

sources with the proper scaling factor to set IOUTFS as stated in

Equation 3.

10

0

0.1

1

10

100

1000

COMP1 CAPACITOR – nF

Figure 42. External COMP1 Capacitor vs. –3 dB Bandwidth

reference amplifier. Since the –3 dB bandwidth corresponds

to the dominant pole, and hence the time constant, the settling

time of the control amplifier to a stepped reference input

response can be approximated.

The optimum distortion performance for any reconstructed

waveform is obtained with a 0.1 µF external capacitor installed.

Thus, if IREF is fixed for an application, a 0.1 µF ceramic chip

capacitor is recommended. Also, since the control amplifier is

optimized for low power operation, multiplying applications

requiring large signal swings should consider using an external

control amplifier to enhance the application’s overall large signal

multiplying bandwidth and/or distortion performance.

There are two methods in which IREF can be varied for a fixed

RSET. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode

voltage of REFIO is varied over its compliance range of 1.25 V

to 0.10 V. REFIO can be driven by a single-supply amplifier or

DAC, thus allowing IREF to be varied for a fixed RSET. Since the

input impedance of REFIO is approximately 1 MΩ, a simple,

low cost R-2R ladder DAC configured in the voltage mode

topology may be used to control the gain. This circuit is shown

in Figure 43 using the AD7524 and an external 1.2 V reference,

the AD1580.

–12–

REV. B

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