SMS8198S2.7 データシートの表示（PDF） - Summit Microelectronics

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SMS8198S2.7

Philips TriMedia™ Processor Companion Supervisor With a 16K-bit 2-wire Serial Memory

Summit Microelectronics 

Camera Audio

SMS8198

WP

TRI_RESET#

SCL

SDA

SMS8198

Tri Media

Processor

VCR/Monitor

TRI_RESET#

System Boot

Block

Audio

Local Reset

Peripheral

Peripheral

PCI_RESET# PCI Bus

2036 ILL16.0

Figure 1. Typical Implementation of the SMS8198 and TriMedia Processor

The boot hardware operation begins with the assertion of

the reset signal TRI_RESET#. The TRI_RESET# output

from the SMS8198 is guaranteed to be valid at VCC -1.0V.

The reset output is asserted whenever VCC is less than the

VTRIP threshold and will remain asserted after VCC is

>VTRIP for the duration of tPURST. Whenever the

TRI_RESET# is active the memory will be write protected.

In addition to the reset write protection feature, pin 7 can

be tied to a pull-up to disable the write function of the

memory. This effectively turns the memory array into an

inexpensive boot ROM.

After reset is de-asserted, only the system boot block is

allowed to operate. At this point the TriMedia processor

takes over and begins to download data from the memory

array into its system boot block. The data downloaded

contains configuration data to set up the TriMedia proces-

sor and to load special ID information into the PCI configu-

ration space register. The ID information is published in

the PCI configuration register to provide the 16 bit Sub-

system ID and Subsystem Vendor ID.

It should be noted that both the threshold and the tPURST

pulse width are programmable. Not only does this provide

maximum flexibility to the designer, but, as the processor

operating voltage levels migrate downwards, the

SMS8198 can be programmed to following this downward

trend. The values can be selected from the ordering

information table and the devices specified as standard

off-the-shelf items.

2036 5.0 4/18/00

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