LC72122V データシートの表示（PDF） - SANYO -> Panasonic
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LC72122V Datasheet PDF : 22 Pages
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LC72122V
Continued from preceding page.
No.
Control block/data
DO pin control data
DOC0, DOC1, DOC2
Description
• Data that determines DO pin output
DOC2
0
0
0
0
1
1
1
1
DOC1
0
0
1
1
0
0
1
1
DOC0
0
1
0
1
0
1
0
1
DO pin state
Open
Low when the unlock state is detected
end-UC*1
Open
Open
The IO1 pin state*2
The IO2 pin state*2
Open
The open state is selected following a power-on reset.
Note: 1. end-UC: IF counter measurement completion check
(6)
Related data
UL0, UL1,
CTE,
IOC1, IOC2
Unlock detection data
UL0, UL1
(7)
Phase comparator
control data
DZ0, DZ1
(8)
When end-UC is set and an IF count is started (CTE = 0 → 1), the DO pin
automatically goes to the open state.
When the IF count measurement completes, the DO pin goes low and
the count completion check operation is enabled.
The DO pin goes to the open state due to serial data I/O (CE: high).
2. Goes to the open state if the IO pin itself is set to be an output port.
Caution: The DO pin always goes to the open state during the data input period (during the
period when CE is high in mode IN1 or IN2), regardless of the values of the DO pin
control data (DOC0 to DOC2). Also, the DO pin outputs the content of the internal
DO serial data in synchronization with the CL pin signal during the data output period
(during the period when CE is high in the OUT mode) regardless of the values of
the DO pin control data (DOC0 to DOC2).
• Selects the phase error (øE) detection range for PLL lock discrimination.
When a phase error greater than the specified range occurs, the LC72122V determines
that the PLL is unlocked. (*: Don’t care.)
UL1
UL0
øE detection width
Detector output
0
0 Stopped
Open
0
10
øE is output directly
1
* ±6.67 µs
øE is extended by 1 to 2 ms
Note: When unlocked, the DO pin goes low and the serial data output UL bit is 0.
• Phase comparator dead zone control data
DOC0,
DOC1,
DOC2
DZ1
DZ0
0
0 DZA
0
1 DZB
1
0 DZC
1
1 DZD
Dead zone mode
Dead zone width: DZA < DZB < DZC < DZD
(9) Clock time base
TBC
• An 8 Hz 40% duty clock time base signal can be output from BO1 by setting TBC to 1.
(The BO1 data will be ignored.)
Charge pump control data • Data that forcibly controls the charge pump output
DLC
DLC
Charge pump output
0
Normal operation
(10)
1
Forced low
Note: The LC72122V provides a technique for escaping from deadlock by setting Vtune to
VCC (deadlock clear circuit). This is used when the circuit is deadlocked due to the
VCO oscillator being stopped by the VCO control voltage (Vtune) being 0 V.
BO1
Continued on next page.
No. 6113-10/22
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