M64897GP データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M64897GP Datasheet PDF : 8 Pages
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MITSUBISHI ICs (TV)
M64897GP
PLL FREQUENCY SYNTHESIZER WITH DC-DC CONVERTER FOR PC
METHOD OF SETTING DATA
The input information to consit of 2 or data of 4bytes to lead to Chip
Address is received in I2C bus receiver. It shows a definition of bus
protocol admitted in the following.
1_STA CA CB BB STO
2_STA CA D1 D2 STO
3_STA CA CB BB D1 D2 STO
4_STA CA D1 D2 CB BB STO
STA : Start condition
STO : Stop condition
CA : Chip address
CB : Control data byte
BB : BandS.W. data byte
D1 : Divider data byte
D2 : Divider data byte
The information of 5 bytes necessary for circuit operation is chip
address and control data, bandS.W. data of 2 bytes and divider byte
of 2 bytes. After the chip address input, 2 or data of 4 bytes are
received. Function bit is contained the first and the third data byte to
distinguish between divider data and control data, band data, and
"0" goes ahead of divider data, and "1" goes ahead of control data,
bandS.W. data.
SDA
SCL
1-7
8
9
S
ADDRESS R/W
STA
CA
ACK
1-7
8
DATA
9
ACK
1-7
8
DATA
9
ACK
P
STO
Write mode format
Address Byte
Devider Byte1
Devider Byte2
Control Byte1
Band SW Byte
Byte
Read mode format
Address Byte
Status Byte1
Byte
MSB
LSB
1
1
0
0
0
MA1 MA0
0
A
0
N14 N13 N12 N11 N10
N9
N8
A
N7
N6
N5
N4
N3
N2
N1
N0
A
1
X
T2
T1
T0
Rsa Rsb
OS
A
X
X
X
X
BS4 BS3 BS2 BS1
A
MSB
LSB
1
1
0
0
0
MA1 MA0
1
A
POR FL
X
X
X
A2
A1
A0
A
5
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