LTC1420I データシートの表示（PDF） - Linear Technology

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LTC1420I

12-Bit, 10Msps, Sampling ADC

Linear Technology 

LTC1420

POWER REQUIRE E TS The q denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.

(Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN TYP MAX UNITS

VDD

Positive Supply Voltage

(Note 10)

4.75

5.25

V

OVDD

Output Supply Voltage

(Note 10)

2.7

5.25

V

VSS

Negative Supply Voltage

Dual Supply Mode

Single Supply Mode

– 5.25

– 4.75

V

0

V

IDD

Positive Supply Current

q

48

58

mA

ISS

Negative Supply Current

PD

Power Dissipation

q

1.4

2.5

mA

q

250 300

mW

WU

TI I G CHARACTERISTICS The q denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.

(Note 5)

SYMBOL

fSAMPLE

tCONV

tACQ

tH

tL

tAP

PARAMETER

Maximum Sampling Frequency

Conversion Time

Acquisition Time

CLK High Time

CLK Low Time

Aperature Delay of Sample-and-Hold

CONDITIONS

MIN TYP MAX UNITS

q 0.02

10

MHz

q

70

90

ns

q 10

30

ns

q 20

50

ns

q 20

50

ns

– 250

ps

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to ground with GND and OGND

wired together (unless otherwise noted).

Note 3: When these pin voltages are taken below VSS or above VDD, they

will be clamped by internal diodes. This product can handle input currents

greater than 100mA below VSS or above VDD without latchup.

Note 4: When these pin voltages are taken below VSS they will be clamped

by internal diodes. This product can handle input currents greater than

100mA below VSS without latchup. GAIN is not clamped to VDD. When CLK

is taken above VDD, it will be clamped by an internal diode. The CLK pin

can handle input currents of greater than 100mA above VDD without

latchup.

Note 5: VDD = 5V, VSS = – 5V or 0V, fSAMPLE = 10MHz, tr = tf = 5ns unless

otherwise specified.

Note 6: Dynamic specifications are guaranteed for dual supply operation

with a single-ended + AIN input and – AIN grounded. For single supply

dynamic specifications, refer to the Typical Performance Characteristics.

Note 7: Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 8: Bipolar offset is the offset voltage measured from –0.5LSB

when the output code flickers between 0000 0000 0000 and

1111 1111 1111.

Note 9: Guaranteed by design, not subject to test.

Note 10: Recommended operating conditions.

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