LT1641CS8(RevD) データシートの表示（PDF） - Linear Technology
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LT1641CS8 Datasheet PDF : 12 Pages
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LT1641
APPLICATIO S I FOR ATIO
Figure 9. Short-Circuit Waveforms
Figure 11. Automatic Restart Waveforms
VIN
24V
SHORT
PIN
R1
49.9k
1%
R2
3.4k
1%
GND
RS
0.025Ω
Q1
IRF530
R5
10Ω
5%
C1
10nF
D1
CMPZ R3
5248B 59k
1%
VOUT
CL
8
VCC
1
ON
7
SENSE
6
GATE
LT1641
TIMER
5
C2
0.68µF
GND
4
2
FB
3
PWRGD
R7
24k
5%
R4
3.57k
1%
PWRGD
1641 F10
Figure 10. Automatic Restart Application
VIN
24V
SHORT
PIN
R1
49.9k
1%
R2
3.4k
1%
GND
RS
Q1
0.025Ω IRF530
D2
30V
1N5256B
8
VCC
1
ON
D1
R5
CMPZ
10Ω
5248B
5%
C1
R6, 10nF
1k, 5%
76
SENSE GATE
2
FB
LT1641
TIMER
5
C2
0.68µF
GND
4
3
PWRGD
+
VOUT
R3
CL
59k
1%
R7
24k
5%
R4
3.57k
1%
PWRGD
1641 F12
Figure 12. Overvoltage Detection
GATE Pin Voltage
A curve of gate drive vs VCC is shown in Figure 15. The
GATE pin is clamped to a maximum voltage of 18V above
the input voltage. At minimum input supply voltage of 9V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
10
at least 10V and a regular N-FET can be used. In applica-
tions ranges 9V to 24V range, a logic level N-FET must be
used with a proper protection Zener diode between its gate
and source (as D1 shown is Figure 5).
1641fd
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