NJU6624AFG1 データシートの表示（PDF） - Japan Radio Corporation

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NJU6624AFG1

12-CHARACTER 1-LINE DOT MATRIX LCD CONTROLLER DRIVER with SMOOTH SCROLL FUNCTION

Japan Radio Corporation  

gPIN CONFIGURATION

VLCD1

1

VDD

OSC1

P0

P1

P2

P3

REQ

DATA

SCL

CS

RESET

VSS

K0

K1

K2

K3

SEG1/S0

SEG2/S1

SEG3/S2

SEG4/S3

SEG5/S4

SEG6/S5

SEG7/S6

SEG8/S7

NJU6624A/BFG1

NJU6624A/B

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

SEG41

SEG40

SEG39

SEG38

SEG37

SEG36

SEG35

SEG34

gBLOCK DIAGRAM

VLCD1 VLCD2

RB

RB RB

RB

Key scan Circuit

K0 to K3

VLCD V1

V2

V4

(V3)

0SC1

CR OSC Circuit

Power On Reset

VSS

Instruction

Decoder(ID)

LED port

Register

Output

Buffer

Address

Counter

Timing

Gen.

RESET

Reset

Display Data RAM (DD RAM)

14x8bits

REQ

SCL

CS

DATA

Icon Display

RAM

(MK RAM)

12x5bits

Character

Generator

RAM

(CG RAM)

5x7x32bits

Character

Generator

ROM

(CG ROM)

7,840bits

P0 to P3

COM1

to COM7

/COMMK

SEG1

to SEG71

VSS

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