AD744JCHIPS データシートの表示（PDF） - Analog Devices
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AD744JCHIPS Datasheet PDF : 12 Pages
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AD744–SPECIFICATIONS (@ +25؇C and ؎15 V dc, unless otherwise noted)
Model
Conditions
AD744J/A/S
AD744K/B/T
Min
Typ
Max
Min
Typ
Max
INPUT OFFSET VOLTAGE1
Initial Offset
Offset
vs. Temp.
vs. Supply2
vs. Supply
Long-Term Stability
TMIN to TMAX
82
TMIN to TMAX
82
0.3
1.0
2
5
20
95
88
88
15
0.25
0.5
1.0
5
10
100
15
INPUT BIAS CURRENT3
Either Input
Either Input @ TMAX =
J, K
A, B, C
S, T
Either Input
Offset Current
Offset Current @ TMAX =
J, K
A, B, C
S, T
VCM = 0 V
VCM = 0 V
70°C
85°C
125°C
VCM = +10 V
VCM = 0 V
VCM = 0 V
70°C
85°C
125°C
30
100
0.7
2.3
1.9
6.4
31
102
40
150
20
50
0.4
1.1
1.3
3.2
20
52
30
100
0.7
2.3
1.9
6.4
31
102
40
150
10
50
0.2
1.1
0.6
3.2
10
52
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling Time to 0.01%4
Total Harmonic
Distortion
INPUT IMPEDANCE
Differential
Common Mode
G = –1
8
VO = 20 V p-p
G = –1
45
G = –1
f = 1 kHz
R1 ≥ 2 kΩ
VO = 3 V rms
13
9
1.2
75
50
0.5
0.75
0.0003
3 ϫ 1012||5.5
3 ϫ 1012||5.5
13
1.2
75
0.5
0.75
0.0003
3 ϫ 1012||5.5
3 ϫ 1012||5.5
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode
Rejection Ratio
INPUT VOLTAGE NOISE
–11
VCM = ± 10 V
78
TMIN to TMAX
76
VCM = ± 11 V
72
TMIN to TMAX
70
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
± 20
+14.5, –11.5
+13
–11
88
82
84
80
84
78
80
74
2
45
22
18
16
± 20
+14.5, –11.5
+13
88
84
84
80
2
45
22
18
16
INPUT CURRENT NOISE
f = 1 kHz
0.01
0.01
OPEN LOOP GAIN7
OUTPUT CHARACTERISTICS
Voltage
Current
Capacitive Load8
VO = ± 10 V
RLOAD ≥ 2 kΩ
TMIN to TMAX
RLOAD ≥ 2 kΩ
TMIN to TMAX
Short Circuit
Gain = –1
200
400
100
+13, –12.5
± 12
+13.9, –13.3
+13.8, –13.1
25
1000
250
100
+13, –12.5
± 12
400
+13.9, –13.3
+13.8, –13.1
25
1000
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
± 15
± 4.5
3.5
± 18
± 4.5
5.0
± 15
± 18
3.5
4.0
NOTES
1Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2PSRR test conditions: +VS = 15 V, –VS = –12 V to –18 V and +VS = +12 V to +18 V, –VS = –15 V.
3Bias Current Specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
4Gain = –1, RL = 2 k, CL = 10 pF, refer to Figure 25.
5Defined as voltage between inputs, such that neither exceeds ± 10 V from ground.
6Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.
7Open-Loop Gain is specified with VOS both nulled and unnulled.
8Capacitive load drive specified for CCOMP = 20 pF with the device connected as shown in Figure 32. Under these conditions, slew rate = 14 V/µs and 0.01% settling time = 1.5 µs typical.
Refer to Table II for optimum compensation while driving a capacitive load.
Specifications subject to change without notice. All min and max specifications are guaranteed.
Unit
mV
mV
µV/°C
dB
dB
µV/month
pA
nA
nA
nA
pA
pA
nA
nA
nA
MHz
MHz
V/µs
µs
%
Ω||pF
Ω||pF
V
V
V
dB
dB
dB
dB
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V/mV
V/mV
V
V
mA
pF
V
V
mA
–2–
REV.C
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