SN74LS193ML2 データシートの表示（PDF） - ON Semiconductor

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SN74LS193ML2

Presettable 4-Bit Binary Up/down Counter

ON Semiconductor 

SN74LS193

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC P0 MR TCD TCU PL P2 P3

16 15 14 13 12 11 10 9

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1 2 3 4 56 78

P1 Q1 Q0 CPD CPU Q2 Q3 GND

PIN NAMES

CPU

CPD

MR

PL

Pn

Qn

TCD

TCU

Count Up Clock Pulse Input

Count Down Clock Pulse Input

Asynchronous Master Reset (Clear) Input

Asynchronous Parallel Load (Active LOW) Input

Parallel Data Inputs

Flip–Flop Outputs

Terminal Count Down (Borrow) Output

Terminal Count Up (Carry) Output

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

10 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

5 U.L.

5 U.L.

LOGIC SYMBOL

11 15 1 10 9

PL P0 P1 P2 P3

5

CPU

TCU

12

4

CPD

TCD

13

MR Q0 Q1 Q2 Q3

14 3 2 6 7

VCC = PIN 16

GND = PIN 8

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