DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

SN74LS193N データシートの表示(PDF) - ON Semiconductor

部品番号
コンポーネント説明
メーカー
SN74LS193N
ON-Semiconductor
ON Semiconductor ON-Semiconductor
SN74LS193N Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
SN74LS193
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
Input Clamp Diode Voltage
– 0.65 – 1.5
V
VCC = MIN, IIN = – 18 mA
VOH
Output HIGH Voltage
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
0.25 0.4
0.35 0.5
V
IOL = 4.0 mA
V
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
IIH
Input HIGH Current
20
µA VCC = MAX, VIN = 2.7 V
0.1
mA VCC = MAX, VIN = 7.0 V
IIL
Input LOW Current
– 0.4 mA VCC = MAX, VIN = 0.4 V
IOS
Short Circuit Current (Note 1)
– 20
– 100 mA VCC = MAX
ICC
Power Supply Current
34
mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
CPU Input to
TCU Output
CPD Input to
TCD Output
Clock to Q
PL to Q
MR Input to Any Output
Limits
Min Typ Max
25
32
17
26
18
24
16
24
15
24
27
38
30
47
24
40
25
40
23
35
Unit
MHz
ns
ns
ns
ns
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
ts
th
trec
Parameter
Any Pulse Width
Data Setup Time
Data Hold Time
Recovery Time
Limits
Min Typ Max Unit
20
ns
20
ns
5.0
ns
40
ns
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) is defined as the minimum time required
for the correct logic level to be present at the logic input prior
to the PL transition from LOW-to-HIGH in order to be
recognized and transferred to the outputs.
HOLD TIME (th) is defined as the minimum time following
the PL transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the
correct logic level may be released prior to the PL transition
from LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
http://onsemi.com
5

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]